參數(shù)資料
型號: ZL50117GAG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: REFLECTIVE PHOTOSENSOR SMD RSS42
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA324
封裝: 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034, BGA-324
文件頁數(shù): 84/95頁
文件大小: 1157K
代理商: ZL50117GAG
ZL50115/16/17/18/19/20
Data Sheet
84
Zarlink Semiconductor Inc.
Figure 42 - CPU DMA Read - MPC8260
Figure 43 - CPU DMA Write - MPC8260
t
OTV
t
CTV
t
CTV
t
OTV
t
SDV
t
ODV
t
CDV
t
SDV
t
ODV
t
CWV
t
CWV
t
CTH
t
CTS
t
CEH
t
CES
t
CSH
t
CSS
t
CKH
t
CKS
0 or more cycles
t
CC
Note 1: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid
when CPU_TA is asserted (always timed as shown). CPU_DATA will remain valid while CPU_CS and CPU_OE are asserted.
CPU_TA will continue to be driven until CPU_CS is deasserted.
CPU_CS and CPU_OE must BOTH be asserted to enable
the CPU_DATA output.
Note 2: CPU_DREQ1 shown with postive polarity
CPU_SDACK2 shown with negative polarity
CPU_CLK
CPU_DREQ1
CPU_SDACK2
CPU_CS
CPU_OE
CPU_WE
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TA
t
OTV
t
CTV
t
CTV
t
OTV
t
CWV
t
CWV
t
CDH
t
CDS
t
CTH
t
CTS
t
CEH
t
CES
t
CSH
t
CSS
t
CKH
t
CKS
0 or more cycles
t
CC
Note 1: CPU_SDACK1 must be asserted during the cycle shown. It may then be deasserted at any time.
Following assertion of CPU_TA (always timed as shown), CPU_CS may be deasserted. The MPC8260
will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue
to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and
CPU_DATA may be removed.
Note 2: CPU_DREQ0 shown with positive polarity
CPU_SDACK1 shown with negative polarity
CPU_CLK
CPU_DREQ0
CPU_SDACK1
CPU_CS
CPU_OE
CPU_WE
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TA
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