參數(shù)資料
型號: ZL50114GAG2
廠商: XILINX INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA552
封裝: 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552
文件頁數(shù): 111/113頁
文件大?。?/td> 2004K
代理商: ZL50114GAG2
ZL50110/11/12/14
Data Sheet
97
Zarlink Semiconductor Inc.
11.8
CPU Interface Timing
Note 1:
Load = 50 pF maximum
Note 2:
The maximum value of tCTV may cause setup violations if directly connected to the MPC8260. See Section 13.2 for details of
how to accommodate this during board design.
The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of
CPU_TA, not at the positive clock edge during the assertion of CPU_TA.
The CPU_TA maximum assertion time is 4
μs.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
CPU_CLK Period
tCC
15.152
ns
CPU_CLK High Time
tCCH
6ns
CPU_CLK Low Time
tCCL
6ns
CPU_CLK Rise Time
tCCR
4ns
CPU_CLK Fall Time
tCCF
4ns
CPU_ADDR[23:2] Setup Time
tCAS
4ns
CPU_ADDR[23:2] Hold Time
tCAH
2ns
CPU_DATA[31:0] Setup Time
tCDS
4ns
CPU_DATA[31:0] Hold Time
tCDH
2ns
CPU_CS Setup Time
tCSS
4ns
CPU_CS Hold Time
tCSH
2ns
CPU_WE/CPU_OE Setup Time
tCES
5ns
CPU_WE/CPU_OE Hold Time
tCEH
2ns
CPU_TS_ALE Setup Time
tCTS
4ns
CPU_TS_ALE Hold Time
tCTH
2ns
CPU_SDACK1/CPU_SDACK2
Setup Time
tCKS
2ns
CPU_SDACK1/CPU_SDACK2
Hold Time
tCKH
2ns
Note 1
CPU_TA Output Valid Delay
tCTV
2
11.3
ns
Note 1, 2
CPU_DREQ0/CPU_DREQ1
Output Valid Delay
tCWV
26
ns
Note 1
CPU_IREQ0/CPU_IREQ1 Output
Valid Delay
tCRV
26
ns
Note 1
CPU_DATA[31:0] Output Valid
Delay
tCDV
27
ns
Note 1
CPU_CS to Output Data Valid
tSDV
3.2
10.4
ns
CPU_OE to Output Data Valid
tODV
3.3
10.4
ns
CPU_CLK(falling) to CPU_TA
Valid
tOTV
3.2
9.5
ns
Table 42 - CPU Timing Specification
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