參數(shù)資料
型號(hào): ZL50114GAG2
廠商: XILINX INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA552
封裝: 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552
文件頁(yè)數(shù): 100/113頁(yè)
文件大?。?/td> 2004K
代理商: ZL50114GAG2
ZL50110/11/12/14
Data Sheet
87
Zarlink Semiconductor Inc.
Figure 31 - H.110 Timing Diagram
11.3
TDM Interface Timing - H-MVIP
These parameters are based on the Multi-Vendor Integration Protocol (MVIP) specification for an H-MVIP Bus,
Release 1.1a (1997).
Positive transitions of TDM_C2 are synchronous with the falling edges of TDM_C4 and TDM_C16. The signals
TDM_C2, TDM_C4 and TDM_C16 correspond with pins TDM_CLKi. The signals TDM_F0 correspond with pins
TDM_F0i. The signals TDM_HDS correspond with pins TDM_STi and TDM_STo.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
TDM_C2 Period
tC2P
487.8
488.3
488.8
ns
TDM_C2 High
tC2H
220
-
268
ns
TDM_C2 Low
tC2L
220
-
268
ns
TDM_C4 Period
tC4P
243.9
244.1
244.4
ns
TDM_C4 High
tC4H
110
-
134
ns
TDM_C4 Low
tC4L
110
-
134
ns
TDM_C16 Period
tC16P
60.9
61.0
61.1
ns
TDM_C16 High
tC16H
30
-
31
ns
TDM_C16 Low
tC16L
30
-
31
ns
TDM_HDS Output Delay
tPD
--
30
ns
At
8.192 Mbps
TDM_HDS Output Delay
tPD
-
100
ns
At
2.048 Mbps
TDM_HDS Output to HiZ
tHZD
--
30
ns
Table 32 - TDM H-MVIP Timing Specification
tC8P
Ts 127 Bit 8
Ts 0 Bit 1
Ts 0 Bit 2
Ts 127 Bit 8
Ts 0 Bit 1
Ts 0 Bit 2
tDOD
tZDO
tDOZ
tDIV
tDV
t
tFH
tFP
tFS
ttC8L
ttC8H
TDM_C8
TDM_FRAME
TDM_D Input
TDM_D Output
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