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參數資料
| 型號： | ZL50053QCC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP256 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, 0.40 MM PITCH, MS-026BJC, LQFP-256 |
| 文件頁數： | 43/67頁 |
| 文件大?。?/td> | 562K |
| 代理商： | ZL50053QCC |
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ZL50051/3
Data Sheet
43
Zarlink Semiconductor Inc.
13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
Addresses 0063
H
to 0082
H
There are thirty-two Backplane Input Bit Delay Registers (BIDR0 to BIDR31).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and BIDR0 to BIDR31 define the input bit and fractional bit delay of each Backplane stream. The possible
bit delay adjustment is up to 7 3/4 bits, in steps of 1/4 bit.
When the SMPL_MODE bit is HIGH, BIDR0 to BIDR31 define the input bit sampling point as well as the integer bit
delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay
can be adjusted in 1-bit increments from 0 to 7 bits.
The
BIDR0 to BIDR31
registers are configured as follows:
Table 17 - Backplane Input Bit Delay Register (BIDRn) Bits
13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7 3/4 bit periods forward, with resolution of 1/4 bit
period. The default sampling point is at the 3/4 bit location.
This can be described as:
no. of bits delay = BID[4:0] / 4
For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 *
1
/
4
= 4
3
/
4.
When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/4). BID[4:2]
refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from 1/4 to 4/4 in
1/4-bit increments.
BIDRn Bit
(where n = 0 to 31)
Name
Reset
Value
Description
15:5
Reserved
0
Reserved
Must be set to 0 for normal operation
4:0
BID[4:0]
0
Backplane Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 7 3/4).
When SMPL_MODE = HIGH, the binary value of BID[1:0]
refers to the input bit sampling point (1/4 to 4/4). BID[4:2]
refer to the integer bit delay value (0 to 7 bits).
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| ZL50057 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:12 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 48 Inputs and 48 Outputs |
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| ZL50058 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:12 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 48 Inputs and 48 Outputs |
| ZL50058GAC | 制造商:Microsemi Corporation 功能描述:12K DX HI JIT TOI RATE CONC - Trays 制造商:Microsemi Corporation 功能描述:IC DIGITAL SWITCH 12K CH 256PBGA |
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