參數(shù)資料
型號： ZL50053QCC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝： 28 X 28 MM, 1.40 MM HEIGHT, 0.40 MM PITCH, MS-026BJC, LQFP-256
文件頁數(shù)： 42/67頁
文件大?。?/td> 562K
代理商： ZL50053QCC
ZL50051/3
Data Sheet
42
Zarlink Semiconductor Inc.
Table 16 illustrates the bit delay and sampling point selection.
LIDn
SMPL_MODE
= LOW
SMPL_MODE
= HIGH
LID4
LID3
LID2
LID1
LID0
Input Data
Bit Delay
Input Data
Bit Delay
Input Data
Sampling
Point
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (Default)
1/4
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
4
4 1/4
4 1/2
4 3/4
5
5 1/4
5 1/2
5 3/4
6
6 1/4
6 1/2
6 3/4
7
7 1/4
7 1/2
7 3/4
0 (Default)
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
Table 16 - Local Input Bit Delay and Sampling Point Programming Table
相關(guān)PDF資料
PDF描述
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參數(shù)描述
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