參數(shù)資料
型號(hào): ZL50023QCC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 4 K Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝: 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁(yè)數(shù): 66/80頁(yè)
文件大?。?/td> 1341K
代理商: ZL50023QCC
ZL50023
Data Sheet
66
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
Figure 27 - ST-BUS Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps
AC Electrical Characteristics
- ST-BUS/GCI-Bus Input Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
STi Setup Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
t
SIS2
t
SIS4
t
SIS8
t
SIS16
5
5
5
5
ns
ns
ns
ns
2
STi Hold Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
t
SIH2
t
SIH4
t
SIH8
t
SIH16
8
8
8
8
ns
ns
ns
ns
V
TT
V
CT
CKi
FPi
(16.384 MHz)
CKi
FPi
(8.192 MHz)
CKi
FPi
(4.096 MHz)
t
SIS2
t
SIH2
Bit7
Ch0
Bit6
Ch0
t
SIS4
t
SIH4
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit0
Ch63
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
Bit1
Ch127
8.192 Mbps
4.096 Mbps
2.048 Mbps
t
SIS8
t
SIH8
STi0 - 31
STi0 - 31
STi0 - 31
V
CT
V
CT
Bit0
Ch31
Input Frame Boundary
Bit0
Ch127
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