參數(shù)資料
型號： ZL50023QCC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Enhanced 4 K Digital Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝： 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁數(shù)： 31/80頁
文件大?。?/td> 1341K
代理商： ZL50023QCC
ZL50023
Data Sheet
31
Zarlink Semiconductor Inc.
Refer to Figure 20 on page 59, Figure 21 on page 60, Figure 22 on page 61 and Figure 23 on page 62 for the
microprocessor timing.
14.0 Device Reset and Initialization
The RESET pin is used to reset the ZL50023. When this pin is low, the following functions are performed:
synchronously puts the microprocessor port in a reset state
tristates the STio0 - 31 outputs
drives the STOHZ0 - 15 outputs to high
preloads all internal registers with their default values (refer to the individual registers for default values)
clears all internal counters
14.1 Power-up Sequence
The recommended power-up sequence is for the V
DD_IO
supply (normally +3.3 V) to be established before the
power-up of the V
DD_CORE
supply (normally +1.8 V). The V
DD_CORE
supply may be powered up at the same time
as V
DD_IO
, but should not “l(fā)ead” the V
DD_IO
supply by more than 0.3 V.
14.2 Device Initialization on Reset
Upon power up, the ZL50023 should be initialized as follows:
Set the ODE pin to low to disable the STio0 - 31 outputs and to drive STOHZ0 - 15 to high
Set the TRST pin to low to disable the JTAG TAP controller
Reset the device by pulsing the RESET pin to zero for longer than 1
μ
s
After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the
device to stabilize from the power down state before the first microprocessor port access can occur
Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs
Wait at least 500
μ
s prior to the next microport access (see Note below)
Use the block programming mode to initialize the connection memory
Release the ODE pin from low to high after the connection memory is programmed
Note
: If CKi is 16.384 MHz, the waiting time is 500
μ
s; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is
4.096 MHz, the waiting time is 2 ms.
14.3 Software Reset
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset
SRSTSW (bit 1) in the Software Reset Register (SRR).
15.0 Pseudorandom Bit Generation and Error Detection
The ZL50023 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output
streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input
streams. Each transmitter can generate a BER sequence with a pattern of 2
15
-1 pseudorandom code (ITU O.151).
Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1
frame time (125
μ
s). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and
TBEREN (bit 4) in the IMS register. In order to save power, the 32 transmitters and/or receivers can be disabled.
(This is the default state.)
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