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參數(shù)資料
| 型號(hào)： | ZL30414QGC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH Clock Multiplier PLL |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 421K |
| 代理商： | ZL30414QGC |
ZL30414
Data Sheet
11
Zarlink Semiconductor Inc.
3.2 Recommended Interface circuit
3.2.1 LVPECL to LVPECL Interface
The C622oP/N-A, C622oP/N-B, C622oP/N-B, and C622oP/N-D outputs provide differential LVPECL clocks at
622.08 MHz. The LVPECL output drivers require a 50
termination connected to the Vcc-2V source for each
output terminal at the terminating end as shown below. The terminating resistors should be placed as close as
possible to the LVPECL receiver.
Figure 8 - LVPECL to LVPECL Interface
3.2.2 CML to CML Interface
The C155o output provides a differential CML/LVDS compatible clock at 155.52 MHz. The output drivers require a
50
load at the terminating end if the receiver is CML type.
Figure 9 - CML to CML Interface
LVPECL
Receiver
LVPECL
Driver
ZL30414
Z=50
Z=50
C622oP-A
C622oN-A
GND
Typical resistor values: R1 = 130
, R2 =82
R1
R2
VCC=+3.3 V
R1
R2
VCC
0.1 uF
+3.3 V
622.08 MHz
ZL30414
CML
Driver
Z=50
CML
Receiver
50
C155oP
C155oN
GND
VCC
0.1 uF
+3.3 V
50
Z=50
0.1 uF
0.1 uF
Low impedance
DC bias source
155.52 MHz
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| ZL30414QGC1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
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