參數(shù)資料
型號(hào)： ZL30121
廠(chǎng)商： Zarlink Semiconductor Inc.
英文描述： SONET/SDH Low Jitter System Synchronizer
中文描述： SONET / SDH的低抖動(dòng)系統(tǒng)的同步
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 326K
代理商： ZL30121
ZL30121
Data Sheet
7
Zarlink Semiconductor Inc.
K8
p0_fp0
O
Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS).
This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
J7
p0_fp1
O
Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS).
This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz
J10
p1_clk0
O
Programmable Synthesizer 1 - Output Clock 0 (LVCMOS).
This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).
K10
p1_clk1
O
Programmable Synthesizer1 - Output Clock 1 (LVCMOS).
This is a
programmable clock output configurable as a multiple or division of the p1_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 3.088 MHz (2x DS1).
H10
fb_clk
O
Feedback Clock (LVCMOS).
This output is a buffered copy of the feedback
clock for DPLL1. The frequency of this output always equals the frequency of the
selected reference.
E1
dpll2_ref
O
DPLL2 Selected Output Reference (LVCMOS).
This is a buffered copy of the
output of the reference selector for DPLL2. Switching between input reference
clocks at this output is not hitless.
A9
B10
diff0_p
diff0_n
O
Differential Output Clock 0 (LVPECL).
This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 155.52 MHz
A10
B9
diff1_p
diff1_n
O
Differential Output Clock 1 (LVPECL).
This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 622.08 MHz clock
Control
H5
rst_b
I
Reset (LVCMOS, Schmitt Trigger).
A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
J5
dpll1_hs_en
I
u
DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger).
A logic high at
this input enables hitless reference switching. A logic low disables hitless
reference switching and re-aligns DPLL1’s output phase to the phase of the
selected reference input. This feature can also be controlled through software
registers. This pin is internally pulled up to Vdd.
C2
D2
dpll1_mod_sel0
dpll1_mod_sel1
I
u
DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger).
During reset, the levels
on these pins determine the default mode of operation for DPLL1 (Automatic,
Normal, Holdover or Freerun). After reset, the mode of operation can be
controlled directly with these pins, or by accessing the dpll1_modesel register
(0x1F) through the serial interface. This pin is internally pulled up to Vdd.
D1
slave_en
I
u
Master/Slave control (LVCMOS, Schmitt Trigger).
This pin selects the mode of
operation for the device. If set high, slave mode is selected. If set low, master
mode is selected. This feature can also be controlled through software registers.
This pin is internally pulled up to Vdd.
Pin #
Name
I/O
Type
Description
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參數(shù)描述
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ZL30122 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:SONET/SDH Low Jitter Line Card Synchronizer
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