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參數(shù)資料
| 型號： | ZL30120GGG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, 0.80 MM PITCH, LEAD FREE, CABGA-100 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大小： | 309K |
| 代理商： | ZL30120GGG2 |
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ZL30120
Data Sheet
23
Zarlink Semiconductor Inc.
54
apll_clk1_offset90
00
Control register for the apll_clk1 phase position
coarse tuning
R/W
55
apll_offset_fine
00
Control register for the output/output phase
alignment fine tuning for apll path
R/W
56
apll_fp0_freq
05
Control register to select the apll_fp0 frame
pulse frequency
R/W
57
apll_fp0_type
23
Control register to select fp0 type
R/W
58
apll_fp0_offset_0
00
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
59
apll_fp0_offset_1
00
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5A
apll_fp0_offset_2
00
Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
5B
apll_fp1_freq
03
Control register to select apll_fp1 frame pulse
frequency
R/W
5C
apll_fp1_type
03
Control register to select fp1 type
R/W
5D
apll_fp1_offset_0
00
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5E
apll_fp1_offset_1
00
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5F
apll_fp1_offset_2
00
Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
60
reserved
A3
Leave as default
R/W
61
reserved
53
Leave as default
R/W
External Feedback Configuration
62
fb_control
81
Control register to enable fb_clk and the FB
PLL, int/ext feedback select
R/W
63
fb_offset_fine
F5
Control register for the output/output phase
alignment fine tuning
R/W
64
reserved
N * 8 kHz Reference Control
65
ref_freq_mode_0
00
Control register to set whether to use auto
detect, CustomA or CustomB for ref0 to ref3
R/W
66
ref_freq_mode_1
00
Control register to set whether to use auto
detect, CustomA or CustomB for ref4 to ref7
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description
Type
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30121GGG2 | SONET/SDH Low Jitter System Synchronizer |
| ZL30121 | SONET/SDH Low Jitter System Synchronizer |
| ZL30121GGG | SONET/SDH Low Jitter System Synchronizer |
| ZL30122 | SONET/SDH Low Jitter Line Card Synchronizer |
| ZL30122GGG | SONET/SDH Low Jitter Line Card Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30121 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Low Jitter System Synchronizer |
| ZL30121GGG | 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 100CABGA - Trays |
| ZL30121GGG2 | 制造商:Microsemi Corporation 功能描述:PB FREE LOW JITTER SYSTEM SYNCHRONIZER |
| ZL30121GGG2V2 | 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30121GGGV2 | 制造商:Microsemi Corporation 功能描述:LOW JITTER SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:REV 2 LOW JITTER SYSTEM SYNCHRONIZER - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
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