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參數(shù)資料
| 型號： | ZL30120GGG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, 0.80 MM PITCH, LEAD FREE, CABGA-100 |
| 文件頁數(shù)： | 22/27頁 |
| 文件大?。?/td> | 309K |
| 代理商： | ZL30120GGG2 |
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ZL30120
Data Sheet
22
Zarlink Semiconductor Inc.
42
p0_fp0_offset_2
00
Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
43
p0_fp1_freq
05
Control register to select p0_fp1 frame pulse
frequency
R/W
44
p0_fp1_type
11
Control register to select fp1 type
R/W
45
p0_fp1_offset_0
00
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
R/W
46
p0_fp1_offset_1
00
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
R/W
47
p0_fp1_offset_2
00
Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
P1 Configuration Registers
48
p1_enable
83
Control register to enable p1_clk0, p1_clk1, the
P1 synthesizer and select the source
R/W
49
p1_run
03
Control register to generate enable/disable
p1_clk0 and p1_clk1
R/W
4A
p1_freq_0
C1
Control register for the [7:0] bits of the N of
N*8k clk0
R/W
4B
p1_freq_1
00
Control register for the [13:8] bits of the N of
N*8k clk0
R/W
4C
p1_clk0_offset90
00
Control register for the p1_clk0 phase position
coarse tuning
R/W
4D
p1_clk1_div
3F
Control register for the p1_clk1 frequency
selection
R/W
4E
p1_clk1_offset90
00
Control register for the p1_clk1 phase position
coarse tuning
R/W
4F
p1_offset_fine
00
Control register for the output/output phase
alignrment fine tuning
R/W
APLL Configuration Registers
50
apll_enable
8F
Control register to enable apll_clk0, apll_clk1,
apll_fp0, apll_fp1 and the APLL
R/W
51
apll_run
0F
Control register to generate apll_clk0,
apll_clk1, apll_fp0 and apll_fp1
R/W
52
apll_clk_div
42
Control register for the apll_clk0 and apll_clk1
frequency selection
R/W
53
apll_clk0_offset90
00
Control register for the apll_clk0 phase position
coarse tuning
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description
Type
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30121GGG2 | SONET/SDH Low Jitter System Synchronizer |
| ZL30121 | SONET/SDH Low Jitter System Synchronizer |
| ZL30121GGG | SONET/SDH Low Jitter System Synchronizer |
| ZL30122 | SONET/SDH Low Jitter Line Card Synchronizer |
| ZL30122GGG | SONET/SDH Low Jitter Line Card Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30121 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Low Jitter System Synchronizer |
| ZL30121GGG | 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 100CABGA - Trays |
| ZL30121GGG2 | 制造商:Microsemi Corporation 功能描述:PB FREE LOW JITTER SYSTEM SYNCHRONIZER |
| ZL30121GGG2V2 | 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30121GGGV2 | 制造商:Microsemi Corporation 功能描述:LOW JITTER SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:REV 2 LOW JITTER SYSTEM SYNCHRONIZER - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
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