參數(shù)資料
型號： ZL30116
廠商： Zarlink Semiconductor Inc.
英文描述： SONET/SDH OC-48/OC-192 System Synchronizer
中文描述： SONET / SDH的OC-48/OC-192系統(tǒng)同步
文件頁數(shù)： 7/31頁
文件大小： 565K
代理商： ZL30116
ZL30116
Data Sheet
7
Zarlink Semiconductor Inc.
Pin Description
Pin #
Name
I/O
Type
Description
Input Reference
C1
B2
A3
C3
B3
B4
C4
A4
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
I
d
Input References (LVCMOS, Schmitt Trigger).
These are input references
available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight
input references can be automatically or manually selected using software
registers. These pins are internally pulled down to Vss.
B1
A1
A2
sync0
sync1
sync2
I
d
Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).
These are the frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled down to V
ss.
External DPLL Feedback Clock (LVCMOS, Schmitt Trigger).
External
feedback clock input. This allows DPLL1 to adjust for PCB trace propagation
delays. This pin is internally pulled down to Vss. Leave open when not is use.
C5
ext_fb_clk
I
d
B5
ext_fb_fp
I
d
External DPLL Feedback Frame Pulse (LVCMOS, Schmitt Trigger).
External
feedback frame pulse input. This allows DPLL1 to adjust for PCB trace
propagation delays. This pin is internally pulled down to Vss. Leave open when
not is use.
Output Clocks and Frame Pulses
D10
sdh_clk0
O
SONET/SDH Output Clock 0 (LVCMOS).
This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 77.76 MHz.
G10
sdh_clk1
O
SONET/SDH Output Clock 1 (LVCMOS).
This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 19.44 MHz.
E10
sdh_fp0
O
SONET/SDH Output Frame Pulse 0 (LVCMOS).
This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 8 kHz.
F10
sdh_fp1
O
SONET/SDH Output Frame Pulse 1 (LVCMOS).
This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 2 kHz.
K9
p0_clk0
O
Programmable Synthesizer 0 - Output Clock 0 (LVCMOS).
This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
K7
p0_clk1
O
Programmable Synthesizer 0 - Output Clock 1 (LVCMOS).
This is a
programmable clock output configurable as a multiple or division of the p0_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 8.192 MHz.
相關PDF資料
PDF描述
ZL30116GGG SONET/SDH OC-48/OC-192 System Synchronizer
ZL30116GGG2 SONET/SDH OC-48/OC-192 System Synchronizer
ZL30117 SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30117GGG SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30117GGG2 SONET/SDH OC-48/OC-192 Line Card Synchronizer
相關代理商/技術參數(shù)
參數(shù)描述
ZL30116GGG 制造商:Microsemi Corporation 功能描述:
ZL30116GGG2 制造商:Microsemi Corporation 功能描述:
ZL30116GGG2V2 制造商:Microsemi Corporation 功能描述:LOW JITTER SYSTEM SYNCHRONIZER LEAD FREE - Trays 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA
ZL30116GGGV2 制造商:Microsemi Corporation 功能描述:REV 2 LOW JITTER SYSTEM SYNCHRONIZER - Trays 制造商:Microsemi Corporation 功能描述:LOW JITTER SYSTEM SYNCHRONIZER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA
ZL30117 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH OC-48/OC-192 Line Card Synchronizer
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