- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373783 > ZL30116 (Zarlink Semiconductor Inc.) SONET/SDH OC-48/OC-192 System Synchronizer PDF資料下載
參數(shù)資料
| 型號： | ZL30116 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | SONET/SDH OC-48/OC-192 System Synchronizer |
| 中文描述： | SONET / SDH的OC-48/OC-192系統(tǒng)同步 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大?。?/td> | 565K |
| 代理商： | ZL30116 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
ZL30116
Data Sheet
14
Zarlink Semiconductor Inc.
Normal (locked)
The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified
reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency
accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with
the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication
standards.
Holdover
When the DPLL operating in the normal mode loses its reference input, and no other qualified references are
available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data
collected while the DPLL was synchronized. The transition between normal and holdover modes is controlled by
the DPLL so that its initial frequency offset is better than 1 ppb which meets the requirement of Stratum 3E. The
frequency drift after this transition period is dependant on the frequency drift of the external master oscillator.
1.3 Ref and Sync Inputs
There are eight reference clock inputs (
ref0
to
ref7
) available to both DPLL1 and DPLL2. The selected reference
input is used to synchronize the output clocks. Each of the DPLLs have independent reference selectors which can
be controlled using a built-in state machine or set in a manual mode.
Figure 3 - Reference and Sync Inputs
Each of the
ref
inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz.
Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is
within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz
are also available.
2 kHz
16.384 MHz
8 kHz
19.44 MHz
64 kHz
38.88 MHz
1.544 MHz
77.76 MHz
2.048 MHz
6.48 MHz
8.192 MHz
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies
ref7:0
sync2:0
DPLL2
DPLL1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30116GGG | SONET/SDH OC-48/OC-192 System Synchronizer |
| ZL30116GGG2 | SONET/SDH OC-48/OC-192 System Synchronizer |
| ZL30117 | SONET/SDH OC-48/OC-192 Line Card Synchronizer |
| ZL30117GGG | SONET/SDH OC-48/OC-192 Line Card Synchronizer |
| ZL30117GGG2 | SONET/SDH OC-48/OC-192 Line Card Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30116GGG | 制造商:Microsemi Corporation 功能描述: |
| ZL30116GGG2 | 制造商:Microsemi Corporation 功能描述: |
| ZL30116GGG2V2 | 制造商:Microsemi Corporation 功能描述:LOW JITTER SYSTEM SYNCHRONIZER LEAD FREE - Trays 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30116GGGV2 | 制造商:Microsemi Corporation 功能描述:REV 2 LOW JITTER SYSTEM SYNCHRONIZER - Trays 制造商:Microsemi Corporation 功能描述:LOW JITTER SYSTEM SYNCHRONIZER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30117 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH OC-48/OC-192 Line Card Synchronizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。