參數(shù)資料
型號(hào)： ZL30110
廠商： Zarlink Semiconductor Inc.
英文描述： Telecom Rate Conversion DPLL
中文描述： 電信速率轉(zhuǎn)換數(shù)字鎖相環(huán)
文件頁(yè)數(shù)： 6/21頁(yè)
文件大?。?/td> 270K
代理商： ZL30110
ZL30110
Data Sheet
6
Zarlink Semiconductor Inc.
1.2 Pin Description
Pin #
Name
I/O
Type
Description
Input Reference
28
REF
I
Reference (LVCMOS, Schmitt Trigger).
This is the input reference source
used for synchronization. One of four possible frequencies may be used: 8 kHz,
2.048 MHz, 8.192 MHz or 16.384 MHz. This pin is internally pulled down to
GND.
Master Clock
11
OSCi
I
Oscillator Master Clock (Input).
For crystal operation, a 25 MHz crystal is
connected from this pin to OSCo. For clock oscillator operation, this pin must be
connected to a clock source.
10
OSCo
O
Oscillator Master Clock (LVCMOS).
For crystal operation, a 25 MHz crystal is
connected from this pin to OSCi. This output is not suitable for driving other
devices (see C25o output pin for support of such function). For clock oscillator
operation, this pin must be left unconnected.
Control and Status
9
RST
I
Reset (LVCMOS, Schmitt Trigger).
A logic low at this input resets the device.
On power up, the RST pin must be held low for a minimum of 300 ns after the
power supply pins have reached the minimum supply voltage. When the RST
pin goes high, the device will transition into a Reset state for 3 ms. In the
Reset state all outputs will be forced into high impedance.
13
OUT_SEL
I
Output Select (LVCMOS, Schmitt Trigger).
This input pin selects the output
clock frequency of the C100/66o, a logic low selects the 100 MHz output,
while logic high selects the 66 MHz output clock.
3
REF_FAIL
O
Reference Failure Indicator (LVCMOS).
A logic high at this pin indicates that
the REF reference frequency is exhibiting abrupt phase or frequency change.
2
LOCK
O
Lock Indicator (LVCMOS).
This output goes to a logic high when the PLL is
frequency locked to a valid input reference.
Output Clocks
19
C65o
O
Clock 65.536 MHz (LVCMOS).
This output is used in general TDM applications.
The falling edge of this clock is aligned with rising edge of the input reference
(REF).
26
C25ao
O
Clock 25 MHz (LVCMOS).
This is a buffered external oscillator clock, the phase
and frequency accuracy of this output tracks that of the external crystal or
oscillator.
25
C25bo
O
Clock 25 MHz (LVCMOS).
This is a buffered external oscillator clock, the phase
and frequency accuracy of this output tracks that of the external crystal or
oscillator.
24
C25co
O
Clock 25 MHz (LVCMOS).
This is a buffered external oscillator clock, the phase
and frequency accuracy of this output tracks that of the external crystal or
oscillator.
23
C25do
O
Clock 25 MHz (LVCMOS).
This is a buffered external oscillator clock, the phase
and frequency accuracy of this output tracks that of the external crystal or
oscillator.
相關(guān)PDF資料
PDF描述
ZL30110LDE Telecom Rate Conversion DPLL
ZL30110LDE1 Telecom Rate Conversion DPLL
ZL30111 POTS Line Card PLL
ZL30111QDG POTS Line Card PLL
ZL30111QDG1 POTS Line Card PLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30110LDE 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:PLL FREQ SYNTHESIZER TRIPLE 32QFN - Rail/Tube
ZL30110LDE1 制造商:Microsemi Corporation 功能描述:
ZL30110LDF1 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Tape and Reel
ZL30110LDG1 制造商:Microsemi Corporation 功能描述:PB FREE TELECOM RATE CONVERSION DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DPLL RATE CONVERSION 32QFN 制造商:Microsemi Corporation 功能描述:IC DPLL RATE CONVERSION 32QFN
ZL30111 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:POTS Line Card PLL
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*