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參數(shù)資料
| 型號： | ZL30106QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/PDH Network Interface DPLL |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.0 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 1001K |
| 代理商： | ZL30106QDG1 |
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ZL30106
Data Sheet
15
Zarlink Semiconductor Inc.
Figure 8 - REF_SYNC Monitor Circuit
3.3 Time Interval Error (TIE) Corrector Circuit
The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the
recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it recovers from Holdover mode.
The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This
results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown
in Figure 23. The speed of the phase alignment correction is limited by the loop filter bandwidth. Convergence is
always in the direction of least phase travel. TIE_CLR can be kept low continuously. In that case the output clocks
will always align with the selected input reference. This is illustrated in Figure 9.
REF_SYNC
Ratio
Monitor
to DPLL
REF_SYNC
REF
frequency
REF
REF_SYNC
frequency
REF_SYNC
Frequency
Detector
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30106 | SONET/SDH/PDH Network Interface DPLL |
| ZL30106QDG | SONET/SDH/PDH Network Interface DPLL |
| ZL30107 | GbE Line Card Synchronizer |
| ZL30107GGG | GbE Line Card Synchronizer |
| ZL30107GGG2 | GbE Line Card Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30107 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:GbE Line Card Synchronizer |
| ZL30107GGG | 制造商:Microsemi Corporation 功能描述: 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA |
| ZL30107GGG2 | 制造商:Microsemi Corporation 功能描述:GBE LINE CARD SYNCHRONIZER 64CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA |
| ZL30108 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Network Interface DPLL |
| ZL30108_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Network Interface DPLL |
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