參數(shù)資料
型號： ZL30105QDG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64
文件頁數(shù)： 19/50頁
文件大?。?/td> 691K
代理商： ZL30105QDG
ZL30105
Data Sheet
19
Zarlink Semiconductor Inc.
3.3 Output Clock and Frame Pulse Selection
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which
are synchronized to one of three reference inputs (REF0, REF1 or REF2). These signals are available in two
groups controlled by the OUT_SEL2:0 pins, see Table 3.
3.4 Modes of Operation
The ZL30105 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are
selected with mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one
mode to the other is controlled by an external controller. The ZL30105 can be configured to automatically select a
valid input reference under control of its internal state machine by setting MODE_SEL1:0 = 11. In this mode of
operation, a state machine controls selection of references (REF0 or REF1) used for synchronization.
3.4.1 Freerun Mode
Freerun mode is typically used when an independent clock source is required, or immediately following system
power-up before network synchronization is achieved.
In Freerun mode, the ZL30105 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals.
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
±
32 ppm output clock
is required, the master clock must also be
±
32 ppm. See Applications - Section 5.2, “Master Clock“.
OUT_SEL2
Generated Clocks
Generated Frame Pulses
0
C2o, C4o, C8o, C16o
F4o, F8o, F16o
1
C2o, C16o, C32, C65o
F16o, F32o, F65o
OUT_SEL1:0
00
C6o
01
C8.4o
10
C34o
11
C44o
Table 3 - Clock and Frame Pulse Selection with OUT_SEL Pin
MODE_SEL1
MODE_SEL0
Mode
0
0
Normal (with automatic Holdover)
0
1
Holdover
1
0
Freerun
1
1
Automatic
(Normal with automatic Holdover and
automatic reference switching)
Table 4 - Operating Modes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30105QDG1 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer
ZL30106 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
ZL30106_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
ZL30106QDG 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH NETWORK INTRFC 64TQFP - Trays 制造商:Microsemi 功能描述:Microsemi ZL30106QDG Communication Misc
ZL30106QDG1 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH NETWORK INTRFC 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE SONET/SDH/PDH NTWK INTERFACEDPLL
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