參數(shù)資料
型號(hào)： ZL20250LCF
廠商： Zarlink Semiconductor Inc.
英文描述： 2.5G Multimode Transceiver
中文描述： 2.5G的多模收發(fā)器
文件頁數(shù)： 16/56頁
文件大小： 392K
代理商： ZL20250LCF
ZL20250
Data Sheet
16
Zarlink Semiconductor Inc.
1.2 Transmit
Transmit operation is similar for all modes and a detailed diagram is shown in Figure 7. This diagram also shows the
UHF LO generation circuit blocks. A summary of the characteristics of the transmit path circuit blocks are given in
the table below. All circuit blocks are differential with the exception of the transmit RF outputs.
Differential baseband transmit I and Q signals from a baseband processor are input to the ZL20250. The baseband
signals are passed through filters - the filter bandwidth is selected for the appropriate mode i.e. IS136 or GSM. A
quadrature modulator modulates these baseband signals on to the transmit IF which is typically around 200 MHz.
This modulated IF signal is passed through an on chip low pass filter which removes harmonics of the IF and then
into a gain controlled amplifier. This amplifier is controlled by an external analogue signal and provides greater than
60dB gain control The output of the gain controlled amplifier can then be up-converted to RF or alternatively the
output can be sent to an off chip filter to provide further filtering and removal of noise before up-conversion. This filter
is a parallel tuned circuit as shown in Figure 8. The choice of component values is dependent on the IF frequency
being used. The filter output is then fed back on chip to the up-converter. A SSB mixer is used for the up-conversion
to remove the unwanted image. High side or low side LO injection can be selected
A buffer amplifier after the up-conversion provides a further 9 dB gain control in 3 dB increments. This gain is
programmable via the serial bus and can be used to optimize noise and linearity performance in particular
applications. Finally there are two RF output stages for 900 MHz and 1900 MHz frequency bands. Each RF output
is single ended and requires a simple matching network. The supply current of the output stages is automatically
reduced at low transmit gain control voltages improving the efficiency of the output buffer at low output power levels.
The supply current of the output buffer can also be controlled via the serial bus. This allows the supply current to be
reduced which is particularly useful when using AMPS or GSM where the linearity performance is less critical.
The FM modulation for AMPS can be done using I,Q modulation if available. Alternatively FM modulation can be
applied direct to the transmit IF VCO. The loop bandwidth for the transmit VHF PLL should be low ( ~100 Hz) to
ensure the PLL does not remove the modulation. A dc voltage should be applied across the Tx I+, Tx I- and the Tx
Q+, Tx Q- inputs to switch the modulator and generate an IF carrier signal. With a baseband gain of 0dB a dc voltage
of at least 1.5 volts should be applied; a lower voltage can be used with the baseband gain increased to compensate.
It is assumed that this bias can be provided by the baseband however if this is not possible then the simplest solution
is to connect 200kohm resistors between I+, Q+ inputs and Vcc and 200kohm resistors between I+,Q- inputs and
Circuit
Block
Gain
(dB)
Bandwidth
(If Applicable)
Description
Reconstruction Filters
0 -12
IS136/AMPS
12.5 kHz
GSM
100 kHz
Baseband input stage. Gain is programmable in 3 dB steps from 0 to 12
dB.
Filter bandwidth is selected for IS136/AMPS or GSM.
There is also a by-pass mode so that the baseband I and Q signal can go
direct to the modulator
Quadrature Modulator
Generates a modulated IF signal
Transmit IF
400 MHz
Provides gain control at IF frequency. This stage also includes a low
pass filter to remove harmonics and spurii from modulator output.
This stage also includes a buffered IF output which can be used with an
external IF filter.
Up-converter
SSB up-converter to RF frequency. The IF path includes phase shift
networks for the up-converter. This stage also includes the input circuit
from the optional external IF filter
Transmit RF
The 900 MHz and 1900 MHz RF stages each consist of 2 stages. The
first stage gain be set from -6 to +3 dB in 3 dB steps. Output stage
current is controlled by agc signal to reduce current consumption at low
output power levels. Each output stage requires an external
degeneration inductor
Table 4 - Transmit Circuit blocks
相關(guān)PDF資料
PDF描述
ZL30100QDG1 T1/E1 System Synchronizer
ZL30100 T1/E1 System Synchronizer
ZL30100QDC T1/E1 System Synchronizer
ZL30101QDG1 T1/E1 Stratum 3 System Synchronizer
ZL30101 T1/E1 Stratum 3 System Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL20B 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators
ZL2101ALAF 功能描述:IC REG BUCK SYNC ADJ 6A 36QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 產(chǎn)品培訓(xùn)模塊:MIC23xxx HyperLight Load™ Regulators 標(biāo)準(zhǔn)包裝:5,000 系列:HyperLight Load® 類型:降壓（降壓） 輸出類型:固定 輸出數(shù):1 輸出電壓:1.8V 輸入電壓:2.7 V ~ 5.5 V PWM 型:混合物 頻率 - 開關(guān):4MHz 電流 - 輸出:2A 同步整流器:是 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-VFDFN 裸露焊盤，8-MLF? 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:8-MLF?（2x2） 產(chǎn)品目錄頁面:1094 (CN2011-ZH PDF) 其它名稱:576-3303-2
ZL2101ALAFT 功能描述:IC REG BUCK SYNC ADJ 6A 36QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:降壓（降壓） 輸出類型:兩者兼有 輸出數(shù):1 輸出電壓:5V，1 V ~ 10 V 輸入電壓:3.5 V ~ 28 V PWM 型:電流模式 頻率 - 開關(guān):220kHz ~ 1MHz 電流 - 輸出:600mA 同步整流器:無 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-SSOP（0.154"，3.90mm 寬） 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:16-QSOP
ZL2101ALAFTK 功能描述:IC REG BUCK SYNC ADJ 6A 36QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:降壓（降壓） 輸出類型:兩者兼有 輸出數(shù):1 輸出電壓:5V，1 V ~ 10 V 輸入電壓:3.5 V ~ 28 V PWM 型:電流模式 頻率 - 開關(guān):220kHz ~ 1MHz 電流 - 輸出:600mA 同步整流器:無 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-SSOP（0.154"，3.90mm 寬） 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:16-QSOP
ZL2102 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:6A Digital Integrated Synchronous Step-Down DC/DC Regulator with Auto Compensation
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*