參數(shù)資料
型號(hào): ZL20200LDF
廠商: Zarlink Semiconductor Inc.
英文描述: Dual Band IS136/AMPS Transceiver
中文描述: 雙頻IS136/AMPS收發(fā)器
文件頁(yè)數(shù): 20/51頁(yè)
文件大?。?/td> 485K
代理商: ZL20200LDF
ZL20200
Data Sheet
20
Zarlink Semiconductor Inc.
The maximum value for A is 15 and M must always be greater than A. The VHF PLLs do not have fractional N
capability however it is recommended that they are operated at as high a comparison frequency as allowed by the
chosen frequency plan to minimize spurs levels.
Both VHF synthesizers have lock detection circuits. These operate in the same way as described for the UHF
synthesizer.
1.6 Internal Clock Generation
ZL20200 can use 14.4 MHz or 19.44 MHz reference frequency. The appropriate reference must be programmed
via the serial bus. The clock signals for the switched capacitor filters and FM demodulator are generated from the
reference TCXO signal. The internal divide ratios are switched to give the correct ratio.
Figure 12 - Typical VCO Tank Circuit
1.7 VHF VCO
ZL20200 has two VHF VCOs which operate with the VHF PLLs to provide the IF LO signals for both receive and
transmit IF signals. The oscillators are a differential design and require an external tank circuit. A basic circuit with
varactor is shown in Figure 12. It is recommended to include series resistors (e.g. 43 ohms) in each arm of the tank
circuit to prevent any spurious high frequency oscillation due to parasitic capacitances.
nm
33n
18p
18p
43R
43R
10k
10k
From PLL
Loop
Filter
VCO+
VCO-
相關(guān)PDF資料
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