參數(shù)資料
型號(hào): ZL20200LCE
廠商: Zarlink Semiconductor Inc.
英文描述: Dual Band IS136/AMPS Transceiver
中文描述: 雙頻IS136/AMPS收發(fā)器
文件頁數(shù): 36/52頁
文件大小: 516K
代理商: ZL20200LCE
ZL20200
Data Sheet
36
Zarlink Semiconductor Inc.
2.7 UHF PLL Divider Programming Register - Address 9
Bits 23:11 set M counter value (Bit 23 = MSB)
Bits 10:8 set B counter value - max value = 7 (Bit 10 = MSB)
Bits 8:4 set A counter value - max value = 8 (Bit 7 = MSB)
The A counter is a 4 bit counter to enable correct fractional N operation. Valid values of A are in the range 1 to 8.
Using the 64/65/72/73 four modulus prescaler the divide ratio (N) is given by:
N = 64 * M + 8 * B + A
Values of M, B, A can be easily calculated using the formulae in the synthesizer section.
2.8 UHF PLL Reference Divider and Fractional N Programming Register - Address 10
Bit 23 is unused and should be set to '0'
Bits 22:18 set the fractional N numerator (Bit 22 = MSB)
Bits 17:4 set the Reference counter value (Bit 17 = MSB)
2.9 Receive VHF PLL Divider Programming Register - Address 11
Bits 20:8 set M counter value (Bit 20 = MSB)
Bits 7:4 set A counter value - max value = 15 (Bit 7 = MSB)
Using the 16/17 two modulus prescaler the divide value (N) is given by:
N = 16 * M + A
Values of M, A can be easily calculated using the formulae in the synthesizer section.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
M Counter Value
B Counter Value
A Counter Value
Address
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
1
0
X
Frac N Numerator
UHF PLL Reference Counter Value
Address
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
X
X
X
M Counter Value
A Counter Value
Address
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