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ZL20200
Data Sheet
17
Zarlink Semiconductor Inc.
The synthesizer uses a 4 modulus prescaler with an 'M' counter and 'A' and 'B' swallow counters together with a
fractional N counter in the UHF counter allowing maximum flexibility. The reference counter is a simple 14 bit
counter. All counter values are programmed via the serial bus and programming details are shown in the
programming section. Each of the counters operates as count down. At the start of a count the counters are loaded
with their respective values. The initial prescaler ratio is dependent on the values loaded into the A and B counters;
when both the A and B counters reach zero the prescaler ratio is 64 and then remains until the M counter reaches
zero. The complete process is then repeated.
This can be shown in a simple example where M = 9, A = 4 and B = 2 which gives a total divide ratio of 596. The
count sequence is shown in Figure 9.
Figure 9 - Count Sequence for UHF PLL with 4 Modulus Prescaler
At the start of the count sequence the '+1' and '+8' controls to the prescaler are both asserted and the prescaler
ratio is 73. After 2 cycles only the '+1' control is asserted and the divide ratio is 65. After a further 2 cycles the A
counter reaches zero as well and the prescaler ratio is 64 for the remainder of the count sequence. At the end of the
sequence all counters are reloaded and the sequence repeats.
The total divide ratio (N) for this type of counter is given by
N = 64*M + 8*B + A
M is always greater then A or B
A value of A = 0 does not support fractional N operation. Valid values of A are 1 to 8.
The values of M, B and A can be easily calculated from the total divide ratio as shown below.
M = INT ((N - 1)/64)
B = INT (((N - 1) - 64*M)/8)
A = N - 64*M - 8*B
The value of M must always be greater than A or B.
The maximum value of B is 7.
9
M Counter
A Counter
B Counter
Prescaler
+1 Prescaler
+8 Prescaler
8
7
6
5
4
3
2
1
9
8
4
3
2
1
0
0
0
0
0
4
3
2
1
0
0
0
0
0
0
0
2
1
73
73
65
65
64
64
64
64
64
73
73