參數(shù)資料
型號(hào)： ZL10312QCF
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 消費(fèi)家電
英文描述： Satellite Demodulator
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-64
文件頁(yè)數(shù)： 7/15頁(yè)
文件大?。?/td> 340K
代理商： ZL10312QCF
ZL10312
Data Sheet
7
Zarlink Semiconductor Inc.
1.4 Forward Error Correction
The ZL10312 contains FEC blocks to enable error correction for DVB-S and DSS transmissions. The Viterbi
decoder block can decode the convolutional code with rates 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8. The block features
automatic synchronisation, automatic spectral inversion resolution and automatic code rate detection. The trace
back depth of 128 provides better performance at high code rates and the built-in synchronisation algorithm allows
the Viterbi decoder to lock onto signals with very poor signal-to-noise ratios. A Viterbi bit error rate monitor provides
an indication of the error rate at the QPSK output.
The 24-bit error count register in the Viterbi decoder allows the bit error rate at the output of the QPSK demodulator
to be monitored. The 24-bit bit error count register in the Reed-Solomon decoder allows the Viterbi output bit error
rate to be monitored. The 16-bit uncorrectable packet counter yields information about the output packet error rate.
These three monitors and the QPSK SNR register allow the performance of the device and its individual
components, such as the QPSK demodulator and the Viterbi decoder, to be monitored extensively by the external
microprocessor. The frame/byte align block features a sophisticated synchronisation algorithm to ensure reliable
recovery of DVB and DSS framed data streams under worst case signal conditions. The de-interleaver uses
on-chip RAM and is compatible with the DVB and DSS algorithms. The Reed-Solomon decoder is a truncated
version of the (255, 239) code. The code block size is 204 for DVB and 146 for DSS. The decoder provides a count
of the number of uncorrectable blocks as well as the number of bit errors corrected. The latter gives an indication of
the bit error rate at the output of the Viterbi decoder. In DVB mode, spectrum de-scrambling is performed
compatible with the DVB specification. The final output is a parallel or serial transport data stream; packet sync;
data clock; and a block error signal. The data clock may be inverted under software control.
2.0 Electrical Characteristics
2.1 Recommended Operating Condition
Parameter
Symbol
Min.
Typ.
Max.
Units
Core power supply voltage
CVdd
1.71
1.8
1.89
V
Periphery power supply voltage
Input clock frequency (note
1
)
Vdd
3.13
3.3
3.47
V
1. When not using a crystal, XTI may be driven from an external source over the frequency range shown.
2. The maximum serial clock speed on the primary 2-wire bus is related to the input clock frequency and is limited to 100 kHz with a
4.0 MHz clock.
Fxt1
3.99
16.01
MHz
Crystal oscillator frequency
CLK1 clock frequency
2
(with 10 MHz or above)
Fxt2
9.99
16.01
MHz
Fclk1
400
kHz
Ambient operating temperature
0
70
°C
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ZL10313 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Satellite Demodulator
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