參數(shù)資料
型號(hào)： ZL10311GAC
廠商： Zarlink Semiconductor Inc.
英文描述： Digital Television DVB-T-On-a-Chip Processor
中文描述： 數(shù)字電視的DVB - T -上一芯片處理器
文件頁(yè)數(shù)： 11/40頁(yè)
文件大?。?/td> 352K
代理商： ZL10311GAC
Data Sheet
ZL10310/ZL10311
11
Zarlink Semiconductor Inc.
6.0 ZL10310/ZL10311 388-pin Package Pin Descriptions
This section explains the ZL10310 and ZL10311 device pin functions. The following tables are segmented by signal
functions. Many of the pins listed below have multiple functions, and in these cases there is information on how the
multiplexed function connects to the pin.
Many references are made to register settings throughout the Pin Descriptions. The details of the ZL10310 and
ZL10311 registers can be found in the Hardware Design Manual for the ZL103xx family of Integrated Digital
Television Processors (Publication DM5797), available to customers on request, subject to NDA.
6.1 Pin Types
6.2 Front End Interfaces
I
An Input Type with no designator indicates that the signal must be produced by a device using 3.3V
outputs, and ESD protection is provided. There is no internal pull up, so unused inputs should be
tied high or low.
IO
Pin Type indicates that the pin can be programmed with control bits to be used as an input or an
output.
B
Pin Type indicates that the pin function can alternate between an input and output depending on the
use at that instant i.e. it is Bi-directional. Out characteristics are the same as an Out pin.
OD
is an open drain Output.
O
is a standard 3.3 V, 65 ohm, output, unless otherwise specified. DC drive is 8.2mA/5.4mA @ VH/VL
respectively. Maximum slew rate is 75mA/ns, unless otherwise specified
.
5V
is a 5V tolerant Input or Output. An Input Type with a 5V designator indicates that the input tolerates
5V signals. There is no internal pull up.
Pin Name
Pin
No.
Function
Pin
Type
Description
Notes
ADCCLK
R02
ADCCLK
O
Sampling Clock Output to External Tuner IF
Analog to Digital Converter. Clock = 20.48MHz.
AGC[0]
L02
Tuner AGC control
O 5V
Master AGC Control Output to External TV Tuner
1
AGC[1]
M03
Tuner AGC control
offset
O 5V
Secondary AGC Control Output to External TV
Tuner. Used to provide a differential AGC feed to
external TV Tuner, if required.
1
GPP[0]
L01
Tuner_SCL
O 5V
External TV Tuner Control Bus - Clock Output
1, 6
GPP[1]
N04
Tuner_SDA
B 5V
External TV Tuner Control Bus - Data
Input/Output.
1, 6
EXT_IN[0]
K01
ED1_MDO[7]
(MSB)
I
External Demodulator 1 Digital Input -
Data Bit 7 (MSB)
5, 7
DV2_IN_DATA[7]
(MSB)
I
Reserved
7
RW_TDO
O
Debug Interface - JTAG TDO (Data Out)
3
相關(guān)PDF資料
PDF描述
ZL10311 Digital Television DVB-T-On-a-Chip Processor
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ZL10310DTV-SOC Digital Television DVB-T-On-a-Chip Processor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL10312 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator
ZL10312QCF 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator
ZL10312QCG 制造商:Microsemi Corporation 功能描述:
ZL10312QCG1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator
ZL10312UBH 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator
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