參數(shù)資料
型號(hào): ZL10311
廠商: Zarlink Semiconductor Inc.
英文描述: Digital Television DVB-T-On-a-Chip Processor
中文描述: 數(shù)字電視的DVB - T -上一芯片處理器
文件頁數(shù): 7/40頁
文件大小: 670K
代理商: ZL10311
Data Sheet
ZL10310/ZL10311
7
Zarlink Semiconductor Inc.
4.3 Coded Orthogonal Frequency Division Multiplex (COFDM) Demodulator
The COFDM demodulator is used to demodulate a digitized COFDM modulated IF signal from the TV Tuner, and
ultimately convert the resulting MPEG-2 Transport Stream to the MPEG-2 demultiplexer.
The Digitized IF is converted to a complex Baseband signal centered on zero frequency. It also removes adjacent
channel interference prior to a Time-to-Frequency Fast Fourier Transform (FFT). The resulting signals are then sent
to a digital re-timing block, symbol sync, carrier recovery, and timing recovery. An AGC signal, with a variable mark
space ratio, is provided to control the signal levels in the tuner sections of the receiver. Forward Error Correction
(FEC) is performed by Viterbi decoding of the convolutional coded data, followed by de-interleaving, Reed-Solomon
decoding, and energy dispersal de-randomising. The output is MPEG-2 Transport Stream packets, in byte format.
The COFDM demodulator is fully compliant with the ETSI 300 744 and Digital Television Group (DTG)
specifications. Key features are:
FFT processor operates in 2k and 8k carrier mode.
1
All hierarchical and non-hierarchical constellations.
Automatic digital carrier recovery over a wide range of offsets without the need for AFC
Automatic digital carrier recovery without the need for a VCXO
Common phase error correction
Channel correction using time and frequency filtering
Automatic co - channel protection, frame sync, and fast channel re- acquisition
Internal controller handles all tracking and acquisition
Viterbi decoding with code rates of 1/2, 2/3, 3/4, 5/6, 6/7, and 7/8
Automatic synchronization and code rate detection
Constraint length K = 7
Trace back depth of 128
De-interleaver followed by DVB Reed Solomon error correction
De-randomizer and common interface formatting
4.4 MPEG Audio Decoder
The MPEG Audio Decoder produces dual channel outputs from MPEG -1 or MPEG -2 Transport Streams with a
maximum rate of 640 kbit/sec. It supports sampling rates of 32, 44.1, and 48 KHz, plus the half rate options. All
sampling rates, plus 512/256 Fs, are produced from an internal PLL. A version of the device is available which
produces six channels of audio output for holders of the Dolby
Digital
2
License.
Decodes MPEG-1 and dual channel MPEG-2 audio
Performs MPEG-1 audio parsing and MPEG-2 Packetised Elementary Stream (PES) audio parsing, or
accepts audio elementary streams
Supports 32kHz, 44.1 kHz, and 48 kHz sampling rates plus the half rate options
All sampling rates, plus 512/256 Fs, derived from an internal PLL
64 step audio attenuation with smooth step transitions
SPDIF output meeting IEC1937 specifications
Re-locatable ancillary data region
Audio Clip Mode
Dolby
AC3 option
2
1. For details on 8k carrier performance and use, please consult Zarlink Field Applications
2. The ZL10311 device is awaiting Dolby Certification
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL10311/GAC 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor
ZL10311DTV-SOC 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor
ZL10311GAC 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor
ZL10312 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator
ZL10312QCF 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator