參數(shù)資料
型號(hào)： ZL10039LCG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 消費(fèi)家電
英文描述： Test, Recorder RoHS Compliant: NA
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC28
封裝： 5 X 5 MM, LEAD FREE, MO-220, QFN-28
文件頁(yè)數(shù)： 8/35頁(yè)
文件大?。?/td> 694K
代理商： ZL10039LCG1
ZL10039
Data Sheet
8
Zarlink Semiconductor Inc.
The output of the phase detector feeds a charge pump which combined with an external loop filter integrates the
current pulses to control the varactor voltage. The charge pump current is automatically varied by the VCO control
logic to compensate for VCO gain variations that are dependent on selected sub band. The varactor control voltage
is externally coupled to the oscillator section through the input pin Vvar.
1.4 I
2
C Interface
All programming for the ZL10039 is controlled by an I
2
C data bus and is compatible with 3V3 standard mode
formats.
Data and Clock are fed in on the SDA and SCL lines respectively as defined by I
2
C bus format. The device can
either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into
write mode if it is logic ‘0’, and read mode if it is logic ‘1’. The I
2
C address is fixed at C0 (Write)/C1(Read) in hex
format.
The ZL10039 contains 16 control registers. These registers are read/write registers. These registers are addressed
as sub-addresses on the I
2
C bus. Registers can be addressed as random access single write/read or random
access sequential write and read as shown below.
Random Access Single Write
Random Access Sequential Write
Stop
Random Access Single Read
Random Access Sequential Read
W
Write bit
A
Acknowledge Bit
N
Not Acknowledge
A SLEEP pin is provided. This powers down all sections of the chip including the crystal oscillator and I
2
C interface.
The RF bypass function will be operational in this mode providing it has been previously enabled through the I
2
C
interface.
Stop
Start
Device
Address
W A
Register
Address
N
A
Register
Data
N
A
Stop
Stop
Start
Device
Address
W A
Register
Address
N
A
Register
Data
N
A
Register
Data
N+1
...
Register
Data
N+M
A
Stop
Stop
Start
Device
Address
W A
Register
Address
N
A
Start
Device
Address
R
A
Register
Data
N
N
Stop
Stop
Start
Device
Address
W A
Register
Address
N
A
Start
Device
Address
R
A
Register
Data
N
A
...
Register
Data
N+M
N
Stop
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