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參數(shù)資料
| 型號(hào)： | ZL10039LCG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Test, Recorder RoHS Compliant: NA |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC28 |
| 封裝： | 5 X 5 MM, LEAD FREE, MO-220, QFN-28 |
| 文件頁數(shù)： | 15/35頁 |
| 文件大?。?/td> | 694K |
| 代理商： | ZL10039LCG1 |
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ZL10039
Data Sheet
15
Zarlink Semiconductor Inc.
2.5 General Control Register
This register controls powerdown and general control functions:
The PD bit is the ‘software’ power down control. When this bit is set to 1, all the analogue blocks are powered down
with the exception of the Crystal Oscillator. The I
2
C interface will remain active and can still be used to enable the
RF Bypass.
Setting the SLEEP input pin high also invokes ‘software’ power down with the addition of powering down the Crystal
Oscillator to produce ‘hardware’ power down. The RF Bypass will remain active if it has been previously
programmed on the I
2
C bus. Note that in ‘hardware’ power down, the I
2
C interface does not operate.
The CLR bit re-triggers the power-on-reset function. This resets all register values to their power-on reset default
value. The CLR bit is itself cleared. Note that the chip-wide reset will reset the I
2
C Interface and the current write
sequence used to set this bit will not be acknowledged.
The P0 bit controls the state of the output port according to Table 22.
Bit Field
Name
Default
Type
Description
7
PD
1
R/W
Power Down
6
CLR
0
R/W
Clear and reset logic
5
P0
0
R/W
Port 0 control
4
-
0
R/W
Test Mode
3:0
ZI3:0-
-
R
Zarlink identity code (read only)
Table 21 - Register F
P0
Output Port State
0
Off, high impedance
1
On, current sinking
Table 22 - Output Port States
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