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參數(shù)資料
| 型號(hào)： | ZL10038LDG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | MULTIMETER, DIGITAL; Accuracy, AC voltage range:+/-1.5% rdg + 3 digits; Accuracy, DC current range:+/-2.5% rdg + 3 digits; Accuracy, DC voltage range:+/-1.2% rdg + 3 digits; Accuracy, resistance range:+/-1.5%rdg + 3 digits; Current RoHS Compliant: NA |
| 中文描述： | 數(shù)字衛(wèi)星調(diào)諧器射頻旁路 |
| 文件頁(yè)數(shù)： | 8/38頁(yè) |
| 文件大小： | 939K |
| 代理商： | ZL10038LDG |
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ZL10036
Data Sheet
8
Zarlink Semiconductor Inc.
Pin Description
Pin
Symbol
Direction
Function
Schematics
1
QDC
NA
Q Channel DC offset correction
capacitor. Configuration and value as per
application diagram (see Figure 2)
2
QDC
NA
3
QOUT
Out
Q Channel baseband differential outputs.
AC couple outputs as per applications
diagram (see Figure 2)
4
QOUT
Out
5
VccBB
+5 V voltage supply for Baseband
6
VccBB
+5 V voltage supply for Baseband
7
IOUT
Out
I Channel baseband differential outputs
AC couple outputs as per applications
diagram (Figure 2)
Same configuration as pins 3 &
4
8
IOUT
Out
9
IDC
NA
I Channel DC offset correction capacitor.
Configuration and value as per
application diagram (Figure 2)
Same configuration as pins 1 &
2
10
IDC
NA
11
SLEEP
In
Hardware power down input.
Logic ‘0’ – normal mode.
Logic ‘1’ - analogue sections are
powered down.
This function is OR’ed with the PD
control function, see section 3.1.2
12
SCL
In
I2C serial clock input
13
SDA
Out
I2C serial data input/output
10
μ
A
Signal
Correction
Baseband
Internal
DC
Output
1.2 mA
VccBB
CMOS Digital Input
SLEEP
DIGDEC
500k
500k
Input
only
SDA/SCL
SDA
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