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參數(shù)資料
| 型號： | ZL10038LDG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | MULTIMETER, DIGITAL; Accuracy, AC voltage range:+/-1.5% rdg + 3 digits; Accuracy, DC current range:+/-2.5% rdg + 3 digits; Accuracy, DC voltage range:+/-1.2% rdg + 3 digits; Accuracy, resistance range:+/-1.5%rdg + 3 digits; Current RoHS Compliant: NA |
| 中文描述： | 數(shù)字衛(wèi)星調(diào)諧器射頻旁路 |
| 文件頁數(shù)： | 24/38頁 |
| 文件大小： | 939K |
| 代理商： | ZL10038LDG |
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ZL10036
Data Sheet
24
Zarlink Semiconductor Inc.
3.4.7 RF Bypass Disable (LEN Bit)
The RF bypass function is disabled by setting
LEN
, bit-0 of register byte-4 to a logic ‘1’. By default, this bit is at a
logic ‘0’ at power-up, and therefore the function is enabled. If the function is not required, a power saving of
approximately 15% can be made by setting this bit. See also section 2.3 on page 16.
3.4.8 Output Port Controls (P1 & P0 Bits)
Register bits
P1
and
P0
, bit-7 in register bytes-7 & 5 respectively, control the output port pins, P1 & P0, pin numbers
39 & 24 respectively.
3.4.9 Power Down (PD Bit)
Bit-7 of byte-13 controls the
PD
register bit which is an alternative to the SLEEP pin (see “SLEEP - Pin 11” on
page 19). Setting the
PD
bit to a logic ‘1’ shuts down the analogue sections of the ZL10036 effecting a saving of
about two thirds of the power required for normal operation. A logic ’0’ restores normal operation. With either
hardware or software power-down, all register settings are unaffected.
3.4.10 Logic Reset (CLR Bit)
Bit-1 of byte-13 controls the
CLR
register bit. When set to a logic ‘1’, this self-clearing bit resets the ZL10036 control
logic. Writing a logic ‘0’ has no effect. The following register numbers are reset to their power-on state: 7, 9, 10, 11,
12 & 13. All other register’s contents are unaffected.
3.4.11 Charge Pump Current (C1 & C0 Bits)
Register bits
C1
and
C0
are programmed by setting bits-6 & 5 of register byte-5. These bits determine the charge
pump current that is used on the output of the frequency synthesizer phase detector.
Bit P1 or P0
Port State
Logic State
(if connected to a pull-up)
0
High impedance
1
(reset state)
1
Low impedance to Vee (Gnd)
0
Table 11 - Port Control Bits
C1
C0
Current in μA
Min.
Typ.
Max.
0
0
±160
±210
±290
(reset state)
0
1
±280
±365
±510
1
0
±470
±625
±860
1
1
Not allowed
Table 12 - Charge Pump Currents
相關PDF資料 |
PDF描述 |
|---|---|
| ZL10036 | Digital Satellite Tuner with RF Bypass |
| ZL10036LDF | Digital Satellite Tuner with RF Bypass |
| ZL10036LDF1 | Digital Satellite Tuner with RF Bypass |
| ZL10036LDG | Digital Satellite Tuner with RF Bypass |
| ZL10036LDG1 | Digital Satellite Tuner with RF Bypass |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10039 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCF | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCF1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCG1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
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