參數(shù)資料
型號(hào): ZL10036LDG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 消費(fèi)家電
英文描述: Digital Satellite Tuner with RF Bypass
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC40
封裝: 6 X 6 MM, QFN-40
文件頁數(shù): 23/38頁
文件大?。?/td> 939K
代理商: ZL10036LDG
ZL10036
Data Sheet
23
Zarlink Semiconductor Inc.
3.4.3 Synthesizer Division Ratio (2
14
:2
0
Bits)
The PLL synthesizer interfaces with the LO multiplex output and runs at the desired frequency for down-conversion.
The step size at the desired conversion frequency, is equal to the loop comparison frequency.
The programmable division ratio,
2
14
to
2
0
, required for a desired conversion frequency, can be calculated from the
following formula:
f
step
+
+
(
×
Desired conversion frequency =
where:
f
step
= Fcomp
3.4.4 RF Gain (RFG Bit)
The RF gain is programmed by setting the
RFG
bit, bit-5 of register byte-4 as required. See also Figure 4, “AGC
Control Structure” on page 13.
3.4.5 Baseband Pre-Filter Gain Adjust (BA1:0 Bits)
The baseband pre-filter gain is programmed by setting
BA1:0
, bits-4 & 3 of register byte-4 as required. See also
Figure 4, “AGC Control Structure” on page 13.
3.4.6 Baseband Post-Filter Gain (BG1:0 Bits)
The baseband post-filter gain is programmed by setting
BG1:0
, bits-2 & 1 of register byte-4 as required. See also
Figure 4, “AGC Control Structure” on page 13.
RFG
Gain Adjust (dB)
0
0
(reset state)
1
+4
Table 8 - RFG Register Bit Function
BA1
BA0
Pre-Filter Gain Adjust (dB)
0
0
0.0
(reset state)
0
1
+4.2
1
0
+8.4
1
1
+12.6
Table 9 - BA1/0 Register Bits Function
BG1
BG0
Post-Filter Gain Adjust (dB)
0
0
0.0
(reset state)
0
1
+4.2
1
0
+8.4
1
1
+12.6
Table 10 - BG1/0 Register Bits Function
2
14
2
13
2
12
2
2
2
1
+
2
0
+
)
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