參數(shù)資料
型號(hào)： ZL10036LDG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 消費(fèi)家電
英文描述： Digital Satellite Tuner with RF Bypass
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC40
封裝： 6 X 6 MM, QFN-40
文件頁(yè)數(shù)： 18/38頁(yè)
文件大?。?/td> 939K
代理商： ZL10036LDG
ZL10036
Data Sheet
18
Zarlink Semiconductor Inc.
2.5 Local Oscillator
The LO on the ZL10036 is fully integrated and consists of three oscillator stages. These are arranged such that the
regions of operation for optimum phase noise are contiguous over the required tuning range of 950 to 2150 MHz
and over the specified operating ambient conditions and process spread.
The local oscillators operate at a harmonic of the required frequency and are divided down to the required LO
conversion frequency. The required divider ratio is automatically selected by the LO control logic, hence
programming of the required conversion frequency across the oscillator bands is automatic and requires no
intervention by the user.
Figure 11 - LO Phase Noise Performance
The oscillators are designed to deliver good free running phase noise at 10 kHz offset, therefore the required
integrated phase jitter from the LO can be achieved without the requirement for running with a high comparison
frequency and hence large tuning increment and wide loop bandwidth.
2.6 PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency
reference and loop filter to control a varicap tuned LO, so forming a complete PLL frequency synthesized source.
The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise performance. The loop can also be operated up to
comparison frequencies of 2 MHz enabling application of a wide loop bandwidth for maximizing the close in phase
noise performance. The LO conversion frequency is coupled to the 15-bit divider in the PLL frequency synthesizer.
The output of the programmable divider is fed to the phase comparator where it is compared with the comparison
frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external
reference source. In both cases the reference frequency is divided down to the comparison frequency by the
reference divider, which is programmable into one of 29 ratios as detailed in Table 13 on page 25.
The typical application for the crystal oscillator is contained in Figure 2 on page 2. The output of the phase detector
feeds a charge pump and loop amplifier section. This combined with an external loop filter integrates the current
pulses into the varactor line voltage with an output range of Vee to VccTUNE. The varactor line voltage is externally
coupled to the oscillator section through the input Vvar, enabling application of a third order loop.
Control of the charge pump current can be made as described in Table 12 on page 24.
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
10
100
1000
10000
100000
Frequency offset (log (offset in kHz))
P
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PDF描述
ZL10036LDG1 Digital Satellite Tuner with RF Bypass
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參數(shù)描述
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ZL10037LCG 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass
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