參數(shù)資料
型號(hào): ZL10036LDG1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 消費(fèi)家電
英文描述: Digital Satellite Tuner with RF Bypass
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC40
封裝: 6 X 6 MM, LEAD FREE, QFN-40
文件頁(yè)數(shù): 22/38頁(yè)
文件大?。?/td> 939K
代理商: ZL10036LDG1
ZL10036
Data Sheet
22
Zarlink Semiconductor Inc.
3.4.2 Register Mapping
Byte
Bit No.
Function
7
(MSB)
6
5
4
3
2
1
0
(LSB)
Reset
state
(hex.)
1
1. This is the power-on default register value - recommended operating values may be different, see “4.1” on page 26.
2. This bit is undefined at power up as its level determines different functions for the other bits in this register.
Further information
1
Device address
1
1
0
0
0
MA1 MA0
0
Table 3 on page 20
2
Programmable
Divider
0
2
14
2
13
2
12
2
11
2
10
2
9
2
8
0x00
See 3.4.3 on page 23
3
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
0x00
4
Control Data
1
0
RFG
BA1
BA0
BG1
BG0
LEN
0x80
“3.4.4” to “3.4.7” on p. 24
5
P0
C1
C0
R4
R3
R2
R1
R0
0x00
pp. 24, 24 & 25
6
1
1
0
0
RSD
0
0
0
0xC0
see “3.4.13” on page 25
7
P1
BF6
BF5
BF4
BF3
BF2
BF1
0
0x20
pp. 24 & 25
8
1
1
0
1
0
0
1
1
0xDB
page 26
9
0
0
1
1
0
0
0
0
0x30
page 26
10
1
1
1
0
0
0
0
1
0xE1
page 26
11
U
2
1
1
1
0
1
0
1
0x75/F5
page 26
12
1
1
1
1
0
0
0
0
0xF0
test function only
13
PD
BR4
BR3
BR2
BR1
BR0
CLR
TL
0x28
pp. 24, 25 & 25
Table 6 - Bit Allocations in the Write Registers
Symbol
Definition
Symbol
Definition
2
14
-2
0
Programmable division ratio control bits
MA1,MA0 Variable address bits
BA1-0
Baseband prefilter gain adjust
P0, P1
External switching ports
BF6-1
Baseband bandwidth adjust
PD
Power down
BG1-0
Baseband postfilter gain adjust
R4-R0
Reference division ratio select
BR4-0
Baseband filter FLL reference frequency select RFG
RF programmable gain adjust
C1,C0
Charge pump current select
RSD
Resistor switch disable
CLR
Control logic reset
TL
Buffered LO output select
LEN
RF bypass enable
Table 7 - Key to Table 6
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