參數(shù)資料
型號(hào): ZL10036LDG1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 消費(fèi)家電
英文描述: Digital Satellite Tuner with RF Bypass
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC40
封裝: 6 X 6 MM, LEAD FREE, QFN-40
文件頁(yè)數(shù): 20/38頁(yè)
文件大?。?/td> 939K
代理商: ZL10036LDG1
ZL10036
Data Sheet
20
Zarlink Semiconductor Inc.
3.2 Device Address Selection
Two internal logic levels,
MA1
and
MA0
, can be set to one of four possible logic states by the voltage applied to the
ADD
pin (#16). These four states in turn define four different read and write addresses on the I2C bus, so that as
many as four separate devices can be individually addressed on one bus. This is of particular use in a multi-tuner
environment as required by PVR applications.
3.3 Read Register
The ZL10036 status can be read by addressing the device in its slave transmitter mode by setting the LSB of the
address byte (the R/W bit) to a one. After the master transmits the correct address byte, the ZL10036 will
acknowledge its address, and transmit data in response to further clocks on the SCL input. If the master responds
with an acknowledge and further clocks, the status byte will be retransmitted until such time as the master fails to
send an acknowledge, when the ZL10036 will release the data bus, allowing the master to generate a stop
condition.
The individual bits in the status register have the following meanings:
3.3.1 Power-On Reset Indicator (POR bit)
This bit is set to a logic ‘1’ if the VccDIG supply to the PLL section has dropped below typically 3.6 V, e.g., when the
device is initially turned on. The bit is reset to ‘0’ when the read sequence is terminated by a STOP command.
When the POR bit is high, this indicates that the programmed information may have been corrupted and the device
reset to power up condition.
3.3.2 Frequency & Phase Lock (FL bit)
Bit 6 (FL) indicates whether the synthesizer is phase locked, a logic ‘1’ is present if the device is locked, and a logic
‘0’ if the device is unlocked.
ADD Pin Voltage
MA1
MA0
Write Address
Read Address
Hex.
Dec.
Hex.
Dec.
Vee (0 V or Gnd)
0
0
0xC0
192
0xC1
193
Open circuit
0.5 * DIGDEC (±20%)
1
0
1
0xC2
194
0xC3
195
1. can be programmed with a single 30 k
resistor to DIGDEC
1
0
0xC4
196
0xC5
197
DIGDEC
1
1
0xC6
198
0xC7
199
Table 3 - Address Selection
Bit No.
7
(MSB)
6
5
4
3
2
1
0
(LSB)
Address
1
1
0
0
0
MA1
MA0
1
Status
POR
FL
X
X
X
X
X
X
Table 4 - Read Data Bit Format (MSB is Transmitted First)
相關(guān)PDF資料
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