參數(shù)資料
型號(hào): Z86E72
廠商: ZiLOG, Inc.
英文描述: OTP IR Microcontroller(一次可編程紅外線微控制器)
中文描述: 檢察官辦公室紅外微控制器(一次可編程紅外線微控制器)
文件頁數(shù): 47/75頁
文件大?。?/td> 394K
代理商: Z86E72
Z86E72/73
Zilog
OTP IR Microcontroller
DS97LVO1100
P R E L I M I N A R Y
47
1
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder controlled by
the Interrupt Priority register. An interrupt machine cycle is
activated when an interrupt request is granted. This dis-
ables all subsequent interrupts, saves the Program
Counter and Status Flags, and then branches to the pro-
gram memory vector location reserved for that interrupt.
All Z86E7X interrupts are vectored through locations in the
program memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request register is polled to determine which
of the interrupt requests need service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling, or both edge trig-
gered, and are programmable by the user. The software
can poll to identify the state of the pin.
Programming bits for the Interrupt Edge Select are located
in the IRQ Register (R250), bits D7 and D6 . The configu-
ration is shown in Table 7.
Clock.
The Z86E7X on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, LC,
ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 1 MHz to 8 MHz maximum, with a series resistance
(RS) less than or equal to 100 Ohms. The Z86L7X on-chip
oscillator may be driven with a cost-effective RC network
or other suitable external clock source.
The crystal should be connected across XTAL1 and
XTAL2 using the recommended capacitors (capacitance
greater than or equal to 22 pF) from each pin to ground.
The RC oscillator configuration is an external resistor con-
nected from XTAL1 to XTAL2, with a frequency-setting ca-
pacitor from XTAL1 to ground (Figure 44).
Table 6. Interrupt Types, Sources, and Vectors
Name
IRQ0
Source
/DAV0, IRQ0
Vector
Location
0, 1
Comments
External
(P32), Rising
Falling Edge
Triggered
External
(P33), Falling
Edge
Triggered
External
(P31), Rising
Falling Edge
Triggered
Internal
Internal
IRQ1,
IRQ1
2, 3
IRQ2
/DAV2, IRQ2,
T
IN
4,5
IRQ3
IRQ4
T16
T8
6, 7
8, 9
Table 7. IRQ Register
IRQ
Interrupt Edge
IRQ2 (P31)
F
F
F
R/F
D7
0
0
1
1
D6
0
1
0
1
IRQ0 (P32)
F
R
F
R/F
Notes:
F = Falling Edge
R = Rising Edge
In analog mode, the Stop-Mode Recovery sources selected by
the SMR register are connected to the IRQ1 input. Any of the
Stop-Mode Recovery sources for SMR (except P31, P32, and
P33) can be used to generate IRQ1 (falling edge triggered).
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