
Z86E64
CMOS Z8 OTP Microcontroller
CP96DZ83200
P R E L I M I N A R Y
7
1
External I/O or Memory Read and Write Timing Table
V
CC
= 4.5V to 5.5V
TA = 0
°
C to 70
°
C
12 MHz
16 MHz
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Symbol
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TdAZ(DS)
TwDSR
TwDSW
TdDSR(DR)
ThDR(DS)
TdDS(A)
TdDS(AS)
TdR/W(AS)
TdDS(R/W)
TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay
TdDS(DW)
/DS Rise to Write Data Not Valid Delay
TdA(DR)
Address Valid to Read Data Req’d Valid
TdAS(DS)
/AS Rise to /DS Fall Delay
TdDI(DS)
Data Input Setup to /DS Rise
TdDM(AS)
/DM Valid to /AS Fall Delay
Parameter
Address Valid to /AS Rise Delay
/AS Rise to Address Float Delay
/AS Rise to Read Data Req’d Valid
/AS Low Width
Address Float to /DS Fall
/DS (Read) Low Width
/DS (Write) Low Width
/DS Fall to Read Data Req’d Valid
Read Data to /DS Rise Hold Time
/DS Rise to Address Active Delay
/DS Rise to /AS Fall Delay
R//W Valid to /AS Rise Delay
/DS Rise to R//W Not Valid
Min
35
45
Max
Min
20
30
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
[2,3]
[2,3]
[1,2,3]
[2,3]
220
180
55
0
185
110
35
0
135
80
[1,2,3]
[1,2,3]
[1,2,3]
[2,3]
[2,3]
[2,3]
[2,3]
[2,3]
[2,3]
[2,3]
[1,2,3]
[2,3]
[1,2,3]
[2,3]
130
75
0
45
55
30
35
35
35
0
35
30
20
30
25
30
255
200
55
75
50
40
60
30
Notes:
[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] See clock cycle dependent characteristics.
Standard Test Load
All timing references use 2.0V for a logic 1 and 0.8V for a logic 0.
Clock Dependent Formulas
Symbol
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
Number
1
2
3
4
6
7
8
Equation
0.40TpC + 0.32
0.59TpC – 3.25
2.38TpC + 6.14
0.66TpC – 1.65
2.33TpC – 10.56
1.27TpC + 1.67
1.97TpC – 42.5
10
11
12
13
14
15
16
17
18
19
TdDS(A)
TdDS(AS)
TdR/W(AS)
TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)
TsDI(DS)
TdDM(AS)
0.8TpC
0.59TpC – 3.14
0.4TpC
0.8TpC – 15
0.4TpC
0.88TpC – 19
4TpC – 20
0.91TpC – 10.7
0.8TpC – 10
0.9TpC – 26.3
Clock Dependent Formulas