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參數(shù)資料
| 型號(hào)： | Z85C80 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | SCSCI Serial Communications and Small Computer Interface(雙通道數(shù)字通信控制器) |
| 中文描述： | SCSCI串行通信和小型計(jì)算機(jī)接口（雙通道數(shù)字通信控制器） |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 35K |
| 代理商： | Z85C80 |
Z
ILOG
& S
MALL
C
OMPUTER
I
NTERFACE
Z85C80
SCSCI S
ERIAL
C
OMMUNICATIONS
A
ND
S
MALL
C
OMPUTER
I
NTERFACE
FEATURES
I
Low-Power CMOS
I
Two Independent, 0 to 2.5 Mbit/sec, Full-Duplex
Channels, each with a Separate Crystal Oscillator,
Baud Rate Generator, and Digital Phase-Locked Loop
for Clock Recovery.
I
Multi-Protocol Operation under Program Control;
Programmable for NRZ, NRZI, or FM Data Encoding.
I
Asynchronous Mode with Five to Eight Bits and One,
One and One-Half, or Two Stop Bits Per Character,
Programmable Clock Factor, Break Detection and
Generation; Parity, Overrun, and Framing Error
Detection.
I
Synchronous Mode with Internal or External Character
Synchronization on One or Two Synchronous
Characters and CRC Generation and Checking with
CRC-16 or CRC-CCITT Preset to Either 1s or 0s.
I
SDLC/HDLC Mode with Comprehensive Frame-Level
Control, Automatic Zero Insertion and Deletion, I-Field
Residue Handling, Abort Generation and Detection,
CRC Generation and Checking, and SDLC Loop
Mode Operation.
I
Local Loopback and Auto Echo Modes
I
Supports T1 Digital Trunk.
I
Enhanced DMA Support:
-
10 X 19-Bit Status FIFO
-
14-Bit Byte Counter
I
Supports SCSI ANSI-X3.131-1986 Standard.
I
Arbitration Support
I
DMA or Programmed I/O Data Transfers
I
Supports Normal DMA
I
Memory or I/O Mapped CPU Interface
I
Asynchronous Interface Supports
3 Mbytes/sec
I
Direct SCSI Bus Interface with On-Board 48 mA Drivers
I
Supports Target and Initiator Roles
I
Available in 68-pin PLCC, 10 MHz and 16 MHz, and
100-pin VQFP, 16 MHz
P
RODUCT
B
RIEF
GENERAL DESCRIPTION
The Z85C80 CMOS SCSCI is an industry standard 85C30
dual channel Serial Communication Controller (SCC) and
an industry standard 53C80 Small Computer System Inter-
face (SCSI) integrated into one monolithic Integrated Cir-
cuit. The internal SCC and SCSI share the 8-bit data bus
(D7 through D0) and read and write inputs (/RD and /WR).
The Z85C80 is offered in a 68-pin PLCC package in both
10 MHz and 16 MHz speed grades for the SCC interface,
and in 100-pin VQFP in the 16 MHz speed grade. The SCSI
interface data transfer rate is 3.0 MBytes/sec. With a few
exceptions, all of the internal SCC and SCSI signals are
connected to the outside pins.
The exceptions are:
I
IEI input to SCC is internally connected to VDD.
I
IEO output from SCC is not internally connected (N/C).
I
READY output from SCSI is not internally connect-
ed (N/C).
I
/SYNCB output from the SCC is not internally connect-
ed (N/C).
I
/TRXCA and /CTSA inputs to the SCC are internally
connected.
I
/TRXCB and /CTSB inputs to the SCC are internally
connected.
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