參數(shù)資料
型號(hào)： Z0538001VSC
廠商： ZILOG INC
元件分類： 總線控制器
英文描述： SMALL COMPUTER SYSTEM INTERFACE (SCSI)
中文描述： SCSI BUS CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 4/37頁(yè)
文件大小： 226K
代理商： Z0538001VSC
4
Z5380 SCSI
PS97SCC0100
Z
ILOG
/DB7-/DB0, /DBP
Data Bus Bits, Data Bus Parity Bit (Bi-
directional, Open-drain). These eight data bits (/DB7-/
DB0), plus a parity bit (/DBP) form the data bus. /DB7 is the
most significant bit (MSB) and has the highest priority
during the Arbitration phase. Data parity is odd. Parity is
always generated and optionally checked. Parity is not
valid during Arbitration.
I//O
Input/Output(Bi-directional, Open-drain). I/O is a
signal driven by a Target which controls the direction of
data movement on the SCSI bus. True indicates input to the
Initiator. This signal is also used to distinguish between
Selection and Reselection phases.
/MSG
Message(Bi-directional, Open-drain, Active Low).
This signal is driven by the Target during the Message
phase. This signal is received by the Initiator.
/REQ
Request (Bi-directional, Open-drain, Active Low).
Driven by the Target and received by the Initiator, this
signal indicates a request for a /REQ//ACK data-transfer
handshake.
/RST
SCSI Bus Reset (Bi-directional, Open-drain, Active
Low). This signal indicates a SCSI bus Reset condition.
/SEL
Select Bi-directional, Open-drain, Active Low). This
signal is used by an Initiator to select a Target, or by a
Target to reselect an Initiator.
PIN DESCRIPTION
(Continued)
IRQ
Interrupt Request Output, Active High). IRQ alerts a
microprocessor of an error condition or an event comple-
tion.
READY
Ready(Output, Active High). Ready is used to
control the speed of Block Mode DMA transfers. This
signal goes active to indicate the chip is ready to send/
receive data and remains Low after a transfer until the last
byte is sent or until the DMA Mode bit is reset.
/RESET
Reset(Input, Active Low). /RESET clears all reg-
isters. It has no effect upon the SCSI /RST signal.
SCSI Bus
The following signals are all bi-directional, active Low,
open-drain, with 48 mA sink capability. All pins interface
directly with the SCSI bus.
/ACK
Acknowledge(Bi-directional, Open-drain, Active
Low). Driven by an Initiator, /ACK indicates an acknowl-
edgment for a /REQ//ACK data-transfer handshake. In the
Target role, /ACK is received as a response to the /REQ
signal.
/ATN
Attention (Bi-directional, Open-drain, Active Low).
Driven by an Initiator, received by the Target, /ATN indi-
cates an Attention condition.
/BSY
Busy (Bi-directional, Open-drain, Active Low). This
signal indicates that the SCSI bus is being used and can
be driven by both the Initiator and the Target device.
C//D
Control/Data(Bi-directional, Open-drain). Driven by
the Target and received by the Initiator, C//D indicates
whether Control or Data information is on the Data Bus.
True indicates Control.
FUNCTIONAL DESCRIPTION
implement all or any of the SCSI protocol in software. These
registers are read (written) by activating /CS with an
address on A2-A0 and then issuing an /IOR (/IOW) pulse.
This section describes the operation of the internal regis-
ters (Table 1).
The Z5380 Small Computer System Interface (SCSI) has a
set of eight registers that are controlled by the CPU. By
reading and writing the appropriate registers, the CPU
may initiate any SCSI Bus activity or may sample and
assert any signal on the SCSI Bus. This allows the user to
PS009101-0201
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