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參數(shù)資料
| 型號(hào)： | YKNIFEX4HW |
| 英文描述： | IC APEX 20KE FPGA 100K |
| 中文描述： | 耶洛奈夫參考平臺(tái)硬件設(shè)計(jì)手冊(cè) |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 186K |
| 代理商： | YKNIFEX4HW |
Yellowknife X4 Hardware Reference Manual
Page 11 /22
Motorola Inc.
Unrestricted Distribution Permitted
98 Feb 20
2.8 Hydra
The Hydra ASIC from Apple implements several systems needed for MacOS compliance:
MPIC interrupt controller, MESC SCSI controller, ADB controller, SCC GeoPort control-
ler, and timers. This device requires three special clocks: a standard PCI clock, a 40-
50MHz clock for the SCSI controller, and a 31.3344 MHz clock for the timers, etc.
Since there is no agreed-upon standard for Mac-style connectors on a PC chassis, and
since these devices are not strictly necessary to support Windows-NT nor MacOS, Yel-
lowknife places the ADB and SCC/GeoPort connectors on a dedicated connector card.
This connector physically replaces one of the ISA slots on board. This allows a small
plug-in board to contain the GeoPort drivers for the serial ports, and drivers for the Apple
Desktop Bus (ADB).
The MCCS142236 provides the chassis-internal termination of the SCSI bus. The termi-
nation shares power via the connector for remotely powering termination. This power is
limited to 1A, and is controlled via a self-resetting polyswitch fuse (in compliance with
PC’97 guidelines, no destructive fuses are used).
CHANGES: X4 allows the interrupt signals to bypass the Hydra and connect directly
from the Winbond into the processor. This allows conguring the board for embedded
modes, where the Hydra is not needed.
2.9 Super I/O
The SuperI/O controller is based upon the National PC87308VUL/IBN device, which
contains the serial, parallel, and oppy I/O controllers. The sufx “IBN” indicates that it
contains the “Phoenix BIOS” implementation of the keyboard/mouse controller. Other
parts are available but “IBN” is the current preferred BIOS for MacOS purposes.
The controller is a Plug-and-Play (PnP) device, which allows the internal controllers to be
logically connected to any desired interrupt line. Additionally, this device contains the
advanced power controller (APC), real-time clock (RTC) and a small array of RAM. All
of these latter devices require battery voltage to maintain state while the power is switched
off. This power is taken from the NVRAM battery (see Section 2.12 on page 13). The
NVRAM in the Super I/O is too small for CHRP purposes and must be disabled by the
rmware so as to eliminate interference with the external NVRAM.
The GPIO ports are used to implement miscellaneous status/control information such as:
F_EJECT*
oppy eject control.
SDA/SCK
allows access to DIMM presence detect I2C EEPROMs.
PID(0:2)
allows access to parallel/serial interposer presence detect
information.
C512K*
code can detect size of L2: 256K or 512K.
CHANGES: X4 allows installation of the compatible PC87307 Additionally, unused
GPIO pins now allow access to the PID signals from the processor and to the I2C ports of
the DIMM modules (through programmed I/O).
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