參數(shù)資料
型號(hào): YKNIFEX4HW
英文描述: IC APEX 20KE FPGA 100K
中文描述: 耶洛奈夫參考平臺(tái)硬件設(shè)計(jì)手冊(cè)
文件頁(yè)數(shù): 22/24頁(yè)
文件大?。?/td> 186K
代理商: YKNIFEX4HW
Yellowknife X4 Hardware Reference Manual
Page 6 /22
Motorola Inc.
Unrestricted Distribution Permitted
98 Feb 20
CHANGES: X4 replaces the automatic PLL settings with manual jumpers. This acco-
modates the new PCI/bus speed ratios supported by the MPC106 version 4.0. Processor
bus speeds up to 100 MHz are supported.
2.3 Memory Architecture
The local bus (i.e. processor bus) is the primary interface to all of the system memory. The
MPC106 serves as a memory controller for an array of SDRAM, as also as a ROM con-
troller. The memory data bus is 64-bits wide, with additional bits optional to serve as par-
ity checks (the MPC106 does not support ECC when using SDRAM).
FIGURE 1. Memory Architecture
The MPC106 requires that the processor/cache data bus be separated from the DRAM
array, so a 64-bit memory buffer is required. Because the memory bus may operate at very
high speeds, with potentially high loading (~100 pF), registered transceivers are used. The
design of the Yellowknife X4 memory system is described in great detail in application
note AN17xx, “SDRAM System Design using the MPC106”.
CHANGES: X4 replaces 4 SIMM sockets (which were paired) with 2 DIMM sockets.
The X4 only supports SDRAM, while X2 supported only EDO. X4 is tuned to operate at
83 MHz or above, and uses registered transceivers to accomplish this. To minimize load-
ing at high speeds, the boot ROM has been moved to the ISA bus.
DIMM Memory
SRAM
PowerPC
MPC60X
Grackle
MPC106
DIMM Memory
64 BIT DATA BUS
Registered
ADDR
MacOS ROM
SRAM
TagRAM
Memory
Control
Signals
Tranceivers
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