參數(shù)資料
型號： XRT94L31_07
廠商： Exar Corporation
英文描述： 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
中文描述： 3通道DS3/E3/STS-1給STS-3/STM-1映射器集成電路
文件頁數(shù)： 107/133頁
文件大小： 1014K
代理商： XRT94L31_07
XRT94L31
107
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
1.3
STS-3/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION
1.3.1
STS-3/STM-1 Telecom Bus Interface Timing Information
This section presents the timing requirements for the STS-3/STM-1 Telecom Bus Interface. In particular this
section prsents the following.
1.
Identifies which edge of TxA_CLK in which the TxA_D[7:0], TxA_PL, TxA_C1J1, TxA_ALARM and
TxA_DP output pins are updated on.
The clock to output delays (from the rising edge of TxA_CLK to the instant that the TxA_D[7:0], TxA_PL,
TxA_C1J1, TxA_ALARM and TxA_DP output pins are updated.
Identifies which edge of RxD_CLK that the RxD_D[7:0], RxD_PL, RxD_C1J1, RxD_ALARM and
RxD_DP input pins are sampled on.
The set-up time requirements (from an update in the RxD_D[7:0], RxD_PL, RxD_C1J1, RxD_ALARM
and RxD_DP input signals to the rising edge of RxD_CLK).
The hold-time requirements (from the rising edge of RxD_CLK to a change in the RxD_D[7:0], RxD_PL,
RxD_C1J1, RxD_ALARM and RxD_DP input signals)
1.3.1.1
The Transmit STS-3/STM-1 Telecom Bus Interface Timing
2.
3.
4.
5.
In the Transmit STS-3/STM-1 Telecom Bus Interface, all of the signals (which are output via this Bus Interface)
are updated upon the rising edge of TxA_CLK (19.44MHz clock signal).
Figures
12
and
13
presents an illustration of the waveforms of the signals that will be output via the Transmit
STS-3/STM-1 Telecom Bus Interface, as well as the timing parameter (t1).
N
OTE
:
The value for t1 can be found in
Table 8
.
The TxSBFP input signal is sampled upon the rising edge of TxA_CLK by the Transmit STS-3/STM-1 Telecom
Bus Interface circuitry, as illustrated below in
Figure 13
.
F
IGURE
12. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
OUTPUT
VIA
THE
T
RANSMIT
STS-3/
STM-1 T
ELECOM
B
US
I
NTERFACE
.
t1
TxA_CLK
TxA_D[7:0]
TxA_PL
TxA_C1J1
A2 C1 C1
J1 Data J1
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