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XRT86VL34
137
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.1
NOTE: Register 0x0FN4, 0x0FN5 and 0x0FN6 only work if the LIU is placed in Single Rail mode. If done so, the Framer
block must also be placed in Single Rail mode in Register 0xn101.
0
QRPD_n
RO
0
Quasi-random Pattern Detection Status:
This READ-ONLY bit indicates whether or not the Receive LIU Block
is currently declaring the QRSS Pattern LOCK status.
0 = Indicates that the XRT86VL34 is NOT currently declaring the
QRSS Pattern LOCK.
1 = Indicates that the XRT86VL34 is currently declaring the QRSS
Pattern LOCK.
NOTE: If the QRPDIE bit (bit D0 of register 0x0Fn4) is enabled, any
transition on this bit will generate an Interrupt.
TABLE 112: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR)
HEX ADDRESS: 0X0FN5
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION