TABLE
參數(shù)資料
型號： XRT86VL34IB-F
廠商： Exar Corporation
文件頁數(shù)： 148/155頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 4CH 225BG
標(biāo)準(zhǔn)包裝： 84
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL34
87
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.1
TABLE 78: BLOCK INTERRUPT STATUS REGISTER (BISR)
HEX ADDRESS: 0XnB00
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
For E1 mode only
6
LBCODE
RO
0
Loopback Code Block Interrupt Status
This bit indicates whether or not the Loopback Code block has an
interrupt request awaiting service.
0 - Indicates no outstanding Loopback Code Block interrupt request
is awaiting service
1 - Indicates the Loopback Code block has an interrupt request
awaiting service. Interrupt Service routine should branch to the inter-
rupt source and read the Loopback Code Interrupt Status register
(address 0xnB0A) to clear the interrupt
NOTE:
This bit will be reset to 0 after the microprocessor has
performed a read to the Loopback Code Interrupt Status
Register.
5
RxClkLOS
RO
0
Loss of Recovered Clock Interrupt Status
This bit indicates whether or not the T1 receive framer is currently
declaring the "Loss of Recovered Clock" interrupt.
0 = Indicates that the T1 Receive Framer Block is NOT currently
declaring the "Loss of Recovered Clock" interrupt.
1 = Indicates that the T1 Receive Framer Block is currently declar-
ing the "Loss of Recovered Clock" interrupt.
NOTE: This bit is only active if the clock loss detection feature is
enabled (Register - 0xn100)
4
ONESEC
RO
0
One Second Interrupt Status
This bit indicates whether or not the T1 receive framer block is cur-
rently declaring the "One Second" interrupt.
0 = Indicates that the T1 Receive Framer Block is NOT currently
declaring the "One Second" interrupt.
1 = Indicates that the T1 Receive Framer Block is currently declar-
ing the "One Second" interrupt.
3
HDLC
RO
0
HDLC Block Interrupt Status
This bit indicates whether or not the HDLC block has any interrupt
request awaiting service.
0 = Indicates no outstanding HDLC block interrupt request is await-
ing service
1 = Indicates HDLC Block has an interrupt request awaiting service.
Interrupt Service routine should branch to the interrupt source and
read the corresponding Data LInk Status Registers (address
0xnB06, 0xnB16, 0xnB26, 0xnB10, 0xnB18, 0xnB28) to clear the
interrupt.
NOTE:
This bit will be reset to 0 after the microprocessor has
performed a read to the corresponding Data Link Status
Registers that generated the interrupt.
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