參數(shù)資料
型號: XRT86VL34_1
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 27/63頁
文件大?。?/td> 402K
代理商: XRT86VL34_1
XRT86VL34
24
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RxCHN0_3/
Rx8KHZ0
RxCHN1_3/
Rx8KHZ1
RxCHN2_3/
Rx8KHZ2
RxCHN3_3/
Rx8KHZ3
C10
D18
L16
T14
O
8
Receive Time Slot Octet Identifier Output-Bit 3 (RxCHNn_3)
/ Receive 8KHz Clock Output (Rx8KHZn):
The exact function of these pins depends on whether or not the
receive framer enables the receive fractional/signaling inter-
face, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_3:
These output pins (RxCHNn_4 through RxCHNn_0) reflect the
five-bit binary value of the current time slot being output by the
receive serial interface. System equipment can use the RxCH-
CLKn to sample the five output pins of each channel to identify
the time slot being output on these pins. RxCHNn_3 indicates
Bit 3 of the time slot channel being output.
If receive fractional/signaling interface is enabled -
Rx8KHZn:
These pins output a reference 8KHz clock signal derived from
the MCLKIN input.
N
OTE
:
Receive Fractional/Signaling interface can be enabled
by programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 to ‘1’.
RxCHN0_4/
RxSCLK0
RxCHN1_4/
RxSCLK1
RxCHN2_4/
RxSCLK2
RxCHN3_4/
RxSCLK3
B10
E17
K16
U14
O
8
Receive Time Slot Octet Identifier Output-Bit 4 (RxCHNn_4)
/ Receive Recovered Line Clock Output (RxSCLKn):
The exact function of these pins depends on whether or not the
receive framer enables the receive fractional/signaling inter-
face, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_4:
These output pins (RxCHNn_4 through RxCHNn_0) reflect the
five-bit binary value of the current time slot being output by the
receive serial interface. System equipment can use the RxCH-
CLKn to sample the five output pins of each channel to identify
the time slot being output on these pins. RxCHNn_4 indicates
the Most Significant Bit (MSB) of the time slot channel being
output.
If receive fractional/signaling interface is enabled - Receive
Recovered Line Clock Output (RxSCLKn):
These pins output the recovered T1/E1 line clock (1.544MHz in
T1 mode and 2.048MHz in E1 mode) for each channel.
N
OTE
:
Receive Fractional/Signaling interface can be enabled
by programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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