參數(shù)資料
型號: XRT86VL34_07
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 85/175頁
文件大?。?/td> 904K
代理商: XRT86VL34_07
XRT86VL34
80
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
T
ABLE
64: T
RANSMIT
S
IGNALING
C
ONTROL
R
EGISTER
0-31 (TSCR 0-31) H
EX
A
DDRESS
: 0
X
n340
TO
0
XN
35F
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
A (x)
R/W
See Note
Transmit Signaling bit A or x bit
This bit allows users to provide signaling Bit A for octets 0-31 if
Channel Associated Signaling (CAS) is enabled and if signaling
data is inserted from TSCR register (TxSIGSRC[1:0] = 01 in this
register)
N
OTE
:
Users must write to TSCR0 (Address 0xn340) the correct
CAS alignment bits (0 bits) in order to get CAS SYNC at the
remote terminal. The xyxx bits can be programmed by
writing to TSCR16 (0xn350) and programming the
TxSIGSRC[1:0] bits within this register to ‘b11’.
6
B (y)
R/W
See Note
Transmit Signaling bit B or y bit
This bit allows users to provide signaling Bit B for octets 0-31 if
Channel Associated Signaling (CAS) is enabled and if signaling
data is inserted from TSCR register (TxSIGSRC[1:0] = 01 in this
register)
N
OTE
:
Users must write to TSCR0 (Address 0xn340) the correct
CAS alignment bits (0 bits) in order to get CAS SYNC at the
remote terminal. The xyxx bits can be programmed by
writing to TSCR16 (0xn350) and programming the
TxSIGSRC[1:0] bits within this register to ‘b11’.
5
C (x)
R/W
See Note
Transmit Signaling bit C or x bit
This bit allows users to provide signaling Bit C for octets 0-31 if
Channel Associated Signaling (CAS) is enabled and if signaling
data is inserted from TSCR register (TxSIGSRC[1:0] = 01 in this
register)
N
OTE
:
Users must write to TSCR0 (Address 0xn340) the correct
CAS alignment bits (0 bits) in order to get CAS SYNC at the
remote terminal. The xyxx bits can be programmed by
writing to TSCR16 (0xn350) and programming the
TxSIGSRC[1:0] bits within this register to ‘b11’.
4
D (x)
R/W
See Note
Transmit Signaling bit D or x bit
This bit allows users to provide signaling Bit D in for octets 0-31 if
Channel Associated Signaling (CAS) is enabled and if signaling
data is inserted from TSCR register (TxSIGSRC[1:0] = 01 in this
register)
N
OTE
:
Users must write to TSCR0 (Address 0xn340) the correct
CAS alignment bits (0 bits) in order to get CAS SYNC at the
remote terminal. The xyxx bits can be programmed by
writing to TSCR16 (0xn350) and programming the
TxSIGSRC[1:0] bits within this register to ‘b11’.
3
Reserved
-
See Note
Reserved
2
Reserved
-
See Note
Reserved
相關PDF資料
PDF描述
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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