參數(shù)資料
型號: XRT86VL34_07
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 15/175頁
文件大小: 904K
代理商: XRT86VL34_07
XRT86VL34
10
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
1:0
CSS[1:0]
R/W
01
Clock Source Select
These bits select the timing source for the Transmit E1 Framer block.
These bits can also determine the direction of TxSERCLK, TxSYNC,
and TxMSYNC in base rate operation mode (2.048MHz Clock mode).
In Base Rate (2.048MHz Clock Mode):
T
ABLE
1: C
LOCK
S
ELECT
R
EGISTER
(CSR) H
EX
A
DDRESS
: 0
X
n100
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
N
OTE
:
TxSYNC/TxMSYNC can be programmed as input or output
depending on the setting of SYNC INV bit in Register Address
0xn109, bit 4. Please see Register Description for the
Synchronization Mux Register (SMR - 0xn109).
N
OTES
:
In High-Speed or multiplexed modes, TxSERCLK, TxSYNC,
and TxMSYNC are all configured as INPUTS only.
CSS[1:0]
T
RANSMIT
S
OURCE
FOR
THE
T
RANSMIT
E1 F
RAMER
B
LOCK
D
IRECTION
OF
T
X
SERCLK
00/11
Loop Timing Mode
The recovered line clock is cho-
sen as the timing source.
Output
01
External Timing Mode
The Transmit Serial Input Clock
from the TxSERCLK_n input pin is
chosen as the timing source.
Input
10
Internal Timing Mode
The MCLK PLL is chosen as the
timing source.
Output
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