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參數(shù)資料
| 型號： | XRT86VL32IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | DATACOM, FRAMER, PBGA225 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225 |
| 文件頁數(shù)： | 7/174頁 |
| 文件大小： | 903K |
| 代理商： | XRT86VL32IB |
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XRT86VL32
B
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
T
ABLE
67: R
ECEIVE
U
SER
C
ODE
R
EGISTER
0-31 (RUCR 0-31) H
EX
A
DDRESS
: 0
XN
380
TO
0
XN
39F ..................... 85
T
ABLE
68: R
ECEIVE
S
IGNALING
C
ONTROL
R
EGISTER
0-31 (RSCR 0-31) H
EX
A
DDRESS
: 0
XN
3A0
TO
0
XN
3BF ...................... 86
T
ABLE
69: R
ECEIVE
S
UBSTITUTION
S
IGNALING
R
EGISTER
0-31 (RSSR 0-31) H
EX
A
DDRESS
0
XN
3C0
TO
0
XN
3DF ...................... 88
T
ABLE
70: R
ECEIVE
S
IGNALING
A
RRAY
R
EGISTER
0 - 31 (RSAR 0-31) H
EX
A
DDRESS
: 0X
N
500
TO
0
XN
51F...................... 89
T
ABLE
71: LAPD B
UFFER
0 C
ONTROL
R
EGISTER
(LAPDBCR0) H
EX
A
DDRESS
: 0
XN
600........................................ 90
T
ABLE
72: LAPD B
UFFER
1 C
ONTROL
R
EGISTER
(LAPDBCR1) H
EX
A
DDRESS
: 0
XN
700........................................ 90
T
ABLE
73: PMON R
ECEIVE
L
INE
C
ODE
V
IOLATION
C
OUNTER
MSB (RLCVCU) H
EX
A
DDRESS
: 0
XN
900 ....................... 91
T
ABLE
74: PMON R
ECEIVE
L
INE
C
ODE
V
IOLATION
C
OUNTER
LSB (RLCVCL) H
EX
A
DDRESS
: 0
XN
901....................... 91
T
ABLE
75: PMON R
ECEIVE
F
RAMING
A
LIGNMENT
B
IT
E
RROR
C
OUNTER
MSB (RFAECU) H
EX
A
DDRESS
: 0
XN
902....................... 92
T
ABLE
76: PMON R
ECEIVE
F
RAMING
A
LIGNMENT
B
IT
E
RROR
C
OUNTER
LSB (RFAECL) H
EX
A
DDRESS
: 0
XN
903........................ 92
T
ABLE
77: PMON R
ECEIVE
S
EVERELY
E
RRORED
F
RAME
C
OUNTER
(RSEFC) H
EX
A
DDRESS
: 0
XN
904........................ 93
T
ABLE
78: PMON R
ECEIVE
CRC-4 B
IT
E
RROR
C
OUNTER
- MSB (RSBBECU) H
EX
A
DDRESS
: 0
XN
905........................ 93
T
ABLE
79: PMON R
ECEIVE
CRC-4 B
LOCK
E
RROR
C
OUNTER
- LSB (RSBBECL) H
EX
A
DDRESS
: 0
XN
906 ........................ 93
T
ABLE
80: PMON R
ECEIVE
F
AR
-E
ND
BL
OCK
E
RROR
C
OUNTER
- MSB (RFEBECU) H
EX
A
DDRESS
: 0
XN
907....................... 94
T
ABLE
81: PMON R
ECEIVE
F
AR
E
ND
B
LOCK
E
RROR
C
OUNTER
-LSB (RFEBECL) H
EX
A
DDRESS
: 0
XN
908........................ 94
T
ABLE
82: PMON R
ECEIVE
S
LIP
C
OUNTER
(RSC) H
EX
A
DDRESS
: 0
XN
909..................... 95
T
ABLE
83: PMON R
ECEIVE
L
OSS
OF
F
RAME
C
OUNTER
(RLFC) H
EX
A
DDRESS
: 0
XN
90A...................... 95
T
ABLE
84: PMON R
ECEIVE
C
OF
F
RAME
A
LIGNMENT
C
OUNTER
(RCFAC) H
EX
A
DDRESS
: 0
XN
90B....................... 95
T
ABLE
85: PMON LAPD F
RAME
C
HECK
S
EQUENCE
E
RROR
C
OUNTER
1 (LFCSEC1) H
EX
A
DDRESS
: 0
XN
90C....................... 96
T
ABLE
86: PMON PRBS B
IT
E
RROR
C
OUNTER
MSB (PBECU) H
EX
A
DDRESS
: 0
XN
90D................... 96
T
ABLE
87: PMON PRBS B
IT
E
RROR
C
OUNTER
LSB (PBECL) H
EX
A
DDRESS
: 0
XN
90E................... 96
T
ABLE
88: PMON T
RANSMIT
S
LIP
C
OUNTER
(TSC) H
EX
A
DDRESS
: 0
XN
90F .................... 97
T
ABLE
89: PMON E
XCESSIVE
Z
ERO
V
IOLATION
C
OUNTER
MSB (EZVCU) H
EX
A
DDRESS
: 0
XN
910 ....................... 97
T
ABLE
90: PMON E
XCESSIVE
Z
ERO
V
IOLATION
C
OUNTER
LSB (EZVCL) H
EX
A
DDRESS
: 0
XN
911....................... 97
T
ABLE
91: PMON F
RAME
C
HECK
S
EQUENCE
E
RROR
C
OUNTER
2 (LFCSEC2) H
EX
A
DDRESS
: 0
XN
91C....................... 98
T
ABLE
92: PMON F
RAME
C
HECK
S
EQUENCE
E
RROR
C
OUNTER
3 (LFCSEC3) H
EX
A
DDRESS
: 0
XN
92C....................... 98
T
ABLE
93: B
LOCK
I
NTERRUPT
S
TATUS
R
EGISTER
(BISR) H
EX
A
DDRESS
: 0
XN
B00 ........................ 99
T
ABLE
94: B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(BIER) H
EX
A
DDRESS
: 0
XN
B01 ...................... 101
T
ABLE
95: A
LARM
& E
RROR
I
NTERRUPT
S
TATUS
R
EGISTER
(AEISR) H
EX
A
DDRESS
: 0
XN
B02 ...................... 103
T
ABLE
96: A
LARM
& E
RROR
I
NTERRUPT
E
NABLE
R
EGISTER
(AEIER) H
EX
A
DDRESS
: 0
XN
B03 ...................... 106
T
ABLE
97: F
RAMER
I
NTERRUPT
S
TATUS
R
EGISTER
(FISR) H
EX
A
DDRESS
: 0
XN
B04................... 108
T
ABLE
98: F
RAMER
I
NTERRUPT
E
NABLE
R
EGISTER
(FIER) H
EX
A
DDRESS
: 0
XN
B05 .................... 111
T
ABLE
99: D
ATA
L
INK
S
TATUS
R
EGISTER
1 (DLSR1) H
EX
A
DDRESS
: 0
XN
B06..................... 113
T
ABLE
100: D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
1 (DLIER1) H
EX
A
DDRESS
: 0
XN
B07 ..................... 115
T
ABLE
101: S
LIP
B
UFFER
I
NTERRUPT
S
TATUS
R
EGISTER
(SBISR) H
EX
A
DDRESS
: 0
XN
B08 ................. 117
T
ABLE
102: S
LIP
B
UFFER
I
NTERRUPT
E
NABLE
R
EGISTER
(SBIER) H
EX
A
DDRESS
: 0
XN
B09 ..................... 120
T
ABLE
103: R
ECEIVE
L
OOPBACK
C
ODE
I
NTERRUPT
AND
S
TATUS
R
EGISTER
(RLCISR) H
EX
A
DDRESS
: 0
XN
B0A...................... 122
T
ABLE
104: R
ECEIVE
L
OOPBACK
C
ODE
I
NTERRUPT
E
NABLE
R
EGISTER
(RLCIER) H
EX
A
DDRESS
: 0
XN
B0B.................... 124
T
ABLE
105: R
ECEIVE
SA I
NTERRUPT
S
TATUS
R
EGISTER
(RSAISR) H
EX
A
DDRESS
: 0
XN
B0C.................. 125
T
ABLE
106: R
ECEIVE
SA I
NTERRUPT
E
NABLE
R
EGISTER
(RSAIER) H
EX
A
DDRESS
: 0
XN
B0D................... 128
T
ABLE
107: E
XCESSIVE
Z
ERO
S
TATUS
R
EGISTER
(EXZSR) H
EX
A
DDRESS
: 0
XN
B0E................. 131
T
ABLE
108: E
XCESSIVE
Z
ERO
E
NABLE
R
EGISTER
(EXZER) H
EX
A
DDRESS
: 0
XN
B0F................... 132
T
ABLE
109: R
X
LOS/CRC I
NTERRUPT
S
TATUS
R
EGISTER
(RLCISR) H
EX
A
DDRESS
: 0
XN
B12 ................. 133
T
ABLE
110: R
X
LOS/CRC I
NTERRUPT
E
NABLE
R
EGISTER
(RLCIER) H
EX
A
DDRESS
: 0
XN
B13.................. 135
T
ABLE
111: D
ATA
L
INK
S
TATUS
R
EGISTER
2 (DLSR2) H
EX
A
DDRESS
: 0
XN
B16..................... 136
T
ABLE
112: D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
2 (DLIER2) H
EX
A
DDRESS
: 0
XN
B17 .................... 138
T
ABLE
113: D
ATA
L
INK
S
TATUS
R
EGISTER
3 (DLSR3) H
EX
A
DDRESS
: 0
XN
B26..................... 140
T
ABLE
114: D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
3 (DLIER3) H
EX
A
DDRESS
: 0
XN
B27 ................... 142
T
ABLE
115: LIU C
HANNEL
C
ONTROL
R
EGISTER
0 (LIUCCR0) H
EX
A
DDRESS
: 0
X
0F
N
0.................. 144
T
ABLE
116: E
QUALIZER
C
ONTROL
AND
T
RANSMIT
L
INE
B
UILD
O
UT
............................................................................................... 146
T
ABLE
117: LIU C
HANNEL
C
ONTROL
R
EGISTER
1 (LIUCCR1) H
EX
A
DDRESS
: 0
X
0F
N
1.................. 147
T
ABLE
118: LIU C
HANNEL
C
ONTROL
R
EGISTER
2 (LIUCCR2) H
EX
A
DDRESS
: 0
X
0F
N
2.................. 149
T
ABLE
119: LIU C
HANNEL
C
ONTROL
R
EGISTER
3 (LIUCCR3) H
EX
A
DDRESS
: 0
X
0F
N
3.................. 151
T
ABLE
120: LIU C
HANNEL
C
ONTROL
I
NTERRUPT
E
NABLE
R
EGISTER
(LIUCCIER) H
EX
A
DDRESS
: 0
X
0F
N
4................... 153
T
ABLE
121: LIU C
HANNEL
C
ONTROL
S
TATUS
R
EGISTER
(LIUCCSR) H
EX
A
DDRESS
: 0
X
0F
N
5 .................... 154
T
ABLE
122: LIU C
HANNEL
C
ONTROL
I
NTERRUPT
S
TATUS
R
EGISTER
(LIUCCISR) H
EX
A
DDRESS
: 0
X
0F
N
6.................... 157
T
ABLE
123: LIU C
HANNEL
C
ONTROL
C
ABLE
L
OSS
R
EGISTER
(LIUCCCCR) H
EX
A
DDRESS
: 0
X
0F
N
7 .................... 159
T
ABLE
124: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
1 (LIUCCAR1) H
EX
A
DDRESS
: 0
X
0F
N
8 .................... 159
T
ABLE
125: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
2 (LIUCCAR2) H
EX
A
DDRESS
: 0
X
0F
N
9 .................... 159
T
ABLE
126: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
3 (LIUCCAR3) H
EX
A
DDRESS
: 0
X
0F
N
A.................... 160
T
ABLE
127: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
4 (LIUCCAR4) H
EX
A
DDRESS
: 0
X
0F
N
B.................... 160
T
ABLE
128: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
5 (LIUCCAR5) H
EX
A
DDRESS
: 0
X
0F
N
C.................... 160
T
ABLE
129: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
6 (LIUCCAR6) H
EX
A
DDRESS
: 0
X
0F
N
D.................... 161
T
ABLE
130: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
7 (LIUCCAR7) H
EX
A
DDRESS
: 0
X
0F
N
E.................... 161
T
ABLE
131: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
8 (LIUCCAR8) H
EX
A
DDRESS
: 0
X
0F
N
F .................... 161
T
ABLE
132: LIU G
LOBAL
C
ONTROL
R
EGISTER
0 (LIUGCR0) H
EX
A
DDRESS
: 0
X
0FE0 .................. 162
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