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參數(shù)資料
| 型號： | XRT79L74 |
| 廠商： | Exar Corporation |
| 英文描述： | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | 4 -通道DS3/E3自動柜員機用戶到網(wǎng)絡(luò)接口/ Combo IC對購買力平價 |
| 文件頁數(shù)： | 9/70頁 |
| 文件大?。?/td> | 547K |
| 代理商： | XRT79L74 |
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PRELIMINARY
XRT79L74
REV. P1.0.0
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
7
P
IN
#
N
AME
TYPE
D
ESCRIPTION
GENERAL PURPOSE INPUT AND OUTPUT PINS
U3
N26
W5
R24
DMO1
DMO2
DMO3
DMO4
O
O
O
O
Drive Monitor Output Pins:
For each channel, if the DMO output signal is "High", then it means that the drive
monitor circuitry within the XRT79L74 has not detected any bipolar signals at the
MTIP and MRING inputs (or via the Internal Drive Monitor circuit) within the last
128 ± 32 bit periods. If this output signal is "Low", then it means that bipolar sig-
nals are being detected at the MTIP and MRING input pins of the XRT79L74.
W1
W2
W3
W4
GPIO_0
GPIO_1
GPIO_2
GPIO_3
I/O
General Purpose Input/Output Pins:
Each of these pins can be configured to function as either a general-purpose input
or output pin. If a given pin (GPIO_X) is configured to function as an input pin,
then the state of this input pin can be monitored by reading Bit X within the "Oper-
ation General Purpose Pin Data" Register (Address Location = 0x0147).
If a given pin is configured to function as an output pin, then the state of this out-
put pin (GPIO_X) can be controlled by writing the appropriate value into Bit X
within the "Operation General Purpose Pin Data" Register.
Finally, the user can configure a given GPIO_X pin to be an input pin by setting Bit
X, within the "Operation General Purpose Pin Direction Control Register (Address
= 0x014B) to "0". Conversely, the user can configure the GPIO_X pin to be an
output pin by setting Bit X, within the "Operation General Purpose Pin Direction
Control" Register (Address = 0x014B) to "1".
P
IN
#
N
AME
TYPE
D
ESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE PINS
AC4
NibbleIntf
I
Nibble Interface Select Input pin:
This input pin permits the user to configure the Transmit Payload Data
Input Interface and the Receive Payload Data Output Interface blocks to
operate in either the "Serial" or the "Nibble-Parallel" Mode.
Setting this input pin "high" configures each of these blocks to operate in
the Nibble-Parallel Mode. In this mode, the "Transmit Payload Data Input
Interface" block will accept the "outbound" payload data (from the
System-Side terminal equipment) in a "nibble-parallel" manner via the
"TxNib[3:0]" input pins. Further, the Receive Payload Data Output
Interface block will output "inbound" payload data (to the System-Side
terminal equipment) in a "nibble-parallel" via the "RxNib[3:0] output pins.
Setting this input pin "low" configures each of these blocks to operate in
the Serial Mode. In this mode, the Transmit Payload Data Input Interface
block will accept the "outbound" payload data (from the System-Side
terminal equipment) in a "serial" manner via the "TxSer" input pin.
Further, the Receive Payload Data Output Interface block will output the
"inbound" payload data (to the System-Side terminal equipment) in a
serial manner, via the "RxSer" output pin.NOTE:
N
OTE
:
This input pin is only active if the XRT79L74 device has been configured to
operate in the Clear-Channel Framer Mode. The user is advised to tie
this input pin to GND if the user intends to configure the XRT79L74
device to operate in the ATM UNI or PPP Modes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT79L74IB | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000ID | Clock Synchronizer/Adapter for Communications |
| XRT8000 | Clock Synchronizer/Adapter for Communications(用于通訊的時鐘同步設(shè)備/調(diào)整器) |
| XRT8001 | WAN Clock for T1 and E1 Systems |
| XRT8001ID | WAN Clock for T1 and E1 Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT79L74IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000D | 制造商:EXAR 制造商全稱:EXAR 功能描述:CLOCK SYNCHRONIZER/ADAPTER FOR COMMUNICATIONS |
| XRT8000ES | 功能描述:鎖相環(huán) - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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