參數(shù)資料
型號： XRT75L04DIVTR-F
廠商： Exar Corporation
文件頁數(shù)： 45/98頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 4CH 176TQFP
標準包裝： 1,000
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 4/4
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 176-LQFP
供應商設備封裝： 176-TQFP（24x24）
包裝： 帶卷 (TR)
á
XRT75L04D
REV. 1.0.1
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2
5.1 AGC/EQUALIZER: .......................................................................................................................................... 30
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 30
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1 ...................................................................................................... 30
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 31
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 31
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3. ................................................................................................................... 31
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ................................................................................................................................. 31
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 32
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 32
DISABLING ALOS/DLOS DETECTION: .......................................................................................................................... 32
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 32
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-1 AP-
PLICATIONS
).......................................................................................................................................................................... 32
FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 ................................................................................................ 33
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775................................................................................................. 33
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 34
6.0 JITTER: ................................................................................................................................................ 35
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 35
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 35
FIGURE 21. JITTER TOLERANCE MEASUREMENTS .................................................................................................................................. 35
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 36
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1 ......................................................................................................................36
FIGURE 23. INPUT JITTER TOLERANCE FOR E3 .................................................................................................................................... 36
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 37
6.3 JITTER GENERATION: .................................................................................................................................. 37
6.4 JITTER ATTENUATOR: ................................................................................................................................. 37
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ......................................................................... 37
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................................................... 37
TABLE 13: JITTER TRANSFER PASS MASKS........................................................................................................................................... 38
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE ...................................................................... 38
7.0 SERIAL HOST INTERFACE: ............................................................................................................... 39
TABLE 14: FUNCTIONS OF SHARED PINS................................................................................................................................................ 39
TABLE 15: REGISTER MAP AND BIT NAMES ........................................................................................................................................... 39
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................................................... 40
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL 0 REGISTERS .................................................................................................... 41
TABLE 18: REGISTER MAP AND BIT NAMES - CHANNEL 1 REGISTERS .................................................................................................... 41
TABLE 19: REGISTER MAP AND BIT NAMES - CHANNEL 2 REGISTERS .................................................................................................... 42
TABLE 20: REGISTER MAP AND BIT NAMES - CHANNEL 3 REGISTERS .................................................................................................... 42
TABLE 21: REGISTER MAP DESCRIPTION .............................................................................................................................................. 43
8.0 DIAGNOSTIC FEATURES: ................................................................................................................. 47
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 47
8.2 LOOPBACKS: ................................................................................................................................................ 48
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 48
FIGURE 25. PRBS MODE ................................................................................................................................................................... 48
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 49
FIGURE 26. ANALOG LOOPBACK ........................................................................................................................................................... 49
8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 50
FIGURE 27. DIGITAL LOOPBACK ............................................................................................................................................................ 50
FIGURE 28. REMOTE LOOPBACK ........................................................................................................................................................... 50
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 51
FIGURE 29. TRANSMIT ALL ONES (TAOS) ............................................................................................................................................ 51
9.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ............................................................... 52
9.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................... 52
FIGURE 30. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ............... 53
9.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 54
9.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 54
9.2.1.1 A BRIEF DESCRIPTION OF AN STS-1 FRAME ......................................................................................................... 54
FIGURE 31. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME ..................................................................................................... 55
FIGURE 32. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
56
FIGURE 33. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 57
FIGURE 34. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 58
9.2.1.2 MAPPING DS3 DATA INTO AN STS-1 SPE ............................................................................................................ 59
FIGURE 35. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE ............................................................................................. 59
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參數(shù)描述
XRT75L04ES 功能描述:時鐘合成器/抖動清除器 4CH T3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L04IV 功能描述:外圍驅(qū)動器與原件 - PCI 4CH E3/DS3/STS1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75L04IV-F 功能描述:外圍驅(qū)動器與原件 - PCI 4-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75L04IVTR 功能描述:時鐘合成器/抖動清除器 4CH E3/DS3/STS1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L04IVTR-F 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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