參數(shù)資料
型號: XRT73R12IB-L
廠商: Exar Corporation
文件頁數(shù): 77/89頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
標準包裝: 40
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 12/12
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 420-LBGA 裸露焊盤
供應商設備封裝: 420-TBGA(35x35)
包裝: 托盤
XRT73R12
76
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
2
LOSMUT Enable
R/W
Muting upon LOS Enable - Channel_n:
This READ/WRITE bit-field is used to configure the Receive Section (within
Channel_n) to automatically pull their corresponding Recovered Data Out-
put pins (e.g., RxPOS_n and RxNEG_n) to GND for the duration that the
Receive Section declares the LOS defect condition. In other words, this fea-
ture (if enabled) will cause the Receive Channel to automatically mute the
Recovered data anytime the Receive Section declares the LOS defect con-
dition.
0 - Disables the Muting upon LOS feature. In this setting the Receive Sec-
tion will NOT automatically mute the Recovered Data whenever it is declar-
ing the LOS defect condition.
1 - Enables the Muting upon LOS feature. In this setting the Receive Sec-
tion will automatically mute the Recovered Data whenever it is declaring the
LOS defect condition.
1
Receive Monitor
Mode Enable
R/W
Receive Monitor Mode Enable - Channel_n:
This READ/WRITE bit-field is used to configure the Receive Section of
Channel_n to operate in the Receive Monitor Mode.
If the user configures the Receive Section to operate in the Receive Monitor
Mode, then it will be able to receive a nominal DSX-3/STSX-1 signal that
has been attenuator by 20dB of flat loss along with 6dB of cable loss, in an
error-free manner. However, internal LOS circuitry is suppressed and LOS
will never assert nor LOS be declared when operating under this mode.
0 - Configures the corresponding channel to operate in the Normal Mode.
1 - Configure the corresponding channel to operate in the Receive Monitor
Mode.
0
Receive Equalizer
Enable
R/W
Receive Equalizer Enable - Channel_n:
This READ/WRITE register bit is used to enable or disable the Receive
Equalizer block within the Receive Section of Channel_n, as listed below.
0 - Disables the Receive Equalizer within the corresponding channel.
1 - Enables the Receive Equalizer within the corresponding channel.
NOTE: For virtually all applications, we recommend that the user set this bit-
field to "1" (for all channels) and enable the Receive Equalizer.
TABLE 37: RECEIVE CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM5
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
相關PDF資料
PDF描述
XRT75L00DIV-F IC LIU E3/DS3/STS-1 SGL 52TQFP
XRT75L00IV-F IC LIU E3/DS3/STS-1 SGL 52TQFP
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XRT75L03DIV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
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