PIN
參數(shù)資料
型號: XRT73R12IB-L
廠商: Exar Corporation
文件頁數(shù): 5/89頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
標準包裝: 40
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 12/12
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 420-LBGA 裸露焊盤
供應商設備封裝: 420-TBGA(35x35)
包裝: 托盤
XRT73R12
10
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
GENERAL CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
P3
TEST
****
Factory Test Mode Input Pin
This pin must be connected to GND for normal operation.
NOTE: This input pin is internally pulled "Low".
AE25
TRST
I
Test Reset
Test Boundary Scan
AB23
TMS
I
Test Mode Select
Test Boundary Scan
AB5
TCK
I
Test Clock
Test Boundary Scan
AB4
TDI
I
Test Data Input
Test Boundary Scan
AE2
TDO
O
Test Data Output
Test Boundary Scan
MICROPROCESSOR PARALLEL INTERFACE -
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
J26
Pmode
I
This pin controls the Microprocessor Parallel Interface mode.
"High" sets a Synchronous clocked interface mode with a clock from the Host.
"Low" sets an Asynchronous mode where a clock internal to the XRT73R12 will
time the operations.
P24
PCLK
I
High speed clock supplied by the Host to provide timing in the Synchronous
Interface mode. This signal must be a square-wave.
N24
CS
I
Chip Select Input (active low)
Initiates a read or write operation. When "High", no parallel communication is
active between the LIU and the Host.
N22
WR
I
Write Input (active low)
Enables the Host to write data D[7:0] into the LIU register space at address
Addr[7:0].
N23
RD
I
Read Input (active low)
Commands the LIU to transfer the contents of a register specified by Addr[7:0]
to the Host.
N25
RDY
O
Ready Line Output (active low)
Provides a handshake between the LIU and the Host that communicates when
an operation has been completed.
NOTE: This pin must be pulled "High" with a 3k
± 1% resistor.
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