參數(shù)資料
型號： XRT73R06
廠商： Exar Corporation
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： 六通道線路接口單元E3/DS3/STS-1
文件頁數(shù)： 4/68頁
文件大?。?/td> 347K
代理商： XRT73R06
XRT73R06
REV. 1.0.0
á
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
1
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
A
PPLICATIONS
.............................................................................................................................................. 1
Figure 1. Block Diagram of the XRT 73R06 ...................................................................................................... 1
ORDERING INFORMATION ................................................................................................................... 1
F
EATURES
.................................................................................................................................................... 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
...................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
........................................................................................................ 2
Figure 2. XRT73R06 in BGA package (Bottom View) ....................................................................................... 3
TABLE OF CONTENTS ................................................................................................................................... 1
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
T
RANSMIT
I
NTERFACE
................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
..................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 8
CONTROL AND ALARM INTERFACE ....................................................................................................... 9
A
NALOG
P
OWER
AND
G
ROUND
................................................................................................................... 12
DIGITAL
P
OWER
AND
G
ROUND
..................................................................................................................... 14
FUNCTIONAL DESCRIPTION ......................................................................................... 16
1.0 R3 Technology (reconfigurable, relayless redundancy) ............................................................... 16
1.1 N
ETWORK
A
RCHITECTURE
................................................................................................................................ 16
Figure 3. Network Redundancy Architecture ................................................................................................. 16
2.0 clock Synthesizer ............................................................................................................................. 17
2.1 C
LOCK
D
ISTRIBUTION
....................................................................................................................................... 17
Figure 5. Clock Distribution Congifured in E3 Mode Without Using SFM ....................................................... 17
Figure 4. Simplified Block Diagram of the Input Clock Circuitry Driving the Microprocessor .......................... 17
3.0 The Transmitter Section .................................................................................................................. 19
Figure 6. Transmit Path Block Diagram .......................................................................................................... 19
3.1 T
RANSMIT
D
IGITAL
I
NPUT
I
NTERFACE
................................................................................................................ 19
Figure 7. Typical interface between terminal equipment and the XRT73R06 (dual-rail data) ......................... 19
Figure 8. Transmitter Terminal Input Timing ................................................................................................... 20
Figure 9. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ........................................... 20
3.2 T
RANSMIT
C
LOCK
............................................................................................................................................ 21
3.3 B3ZS/HDB3 E
NCODER
.................................................................................................................................... 21
3.3.1 B3ZS Encoding ................................................................................................................................... 21
3.3.2 HDB3 Encoding .................................................................................................................................. 21
Figure 10. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 21
Figure 11. B3ZS Encoding Format ................................................................................................................. 21
3.4 T
RANSMIT
P
ULSE
S
HAPER
................................................................................................................................ 22
Figure 13. Transmit Pulse Shape Test Circuit ................................................................................................ 22
3.4.1 Guidelines for using Transmit Build Out Circuit ............................................................................. 22
Figure 12. HDB3 Encoding Format ................................................................................................................. 22
3.5 E3
LINE
SIDE
PARAMETERS
............................................................................................................................... 23
Figure 14. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ................................................... 23
T
ABLE
1: E3 T
RANSMITTER
LINE
SIDE
OUTPUT
AND
RECEIVER
LINE
SIDE
INPUT
SPECIFICATIONS
........................... 24
Figure 15. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications .......... 25
T
ABLE
2: STS-1 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................ 25
T
ABLE
3: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) . 26
Figure 16. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................ 26
T
ABLE
5: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) ..... 27
T
ABLE
4: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................... 27
3.6 T
RANSMIT
D
RIVE
M
ONITOR
............................................................................................................................... 28
3.7 T
RANSMITTER
S
ECTION
O
N
/O
FF
....................................................................................................................... 28
Figure 17. Transmit Driver Monitor set-up. ..................................................................................................... 28
4.0 The Receiver Section ....................................................................................................................... 30
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