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參數(shù)資料
| 型號： | XRT73LC04A |
| 廠商： | Exar Corporation |
| 英文描述： | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | 4通道DS3/E3/STS-1線路接口單元 |
| 文件頁數(shù)： | 41/64頁 |
| 文件大?。?/td> | 360K |
| 代理商： | XRT73LC04A |
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XRT73LC04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
37
When the System Manufacturer is interfacing the Re-
ceive Section of the XRT73LC04A to the Cross-Con-
nect, they should be aware of the following facts:
1.
All DS3 or STS-1 line signals that are present at
either the DSX-3 or the STSX-1 Cross Connect
are required to meet the Isolated Pulse Template
Requirements per Bellcore GR-499-CORE for
DS3 applications, or Bellcore GR-253-CORE for
STS-1 applications.
2.
Bellcore documents state that the amplitude of
these pulses at the DSX-3 or STSX-1 location
can range in amplitude from 360mVpk to
850mVpk.
Bellcore documents stipulate that the Receiving Ter-
minal must be able to receive the pulse template
compliant line signal over a cable length of 0 to 450
feet from the DSX-3 or the STSX-1 Cross-Connect lo-
cation.
These facts are reflected in Figure 23.
Design Considerations for DS3 and STS-1 Appli-
cations
When installing equipment into environments depict-
ed in Figure 23, the system installation personnel
may be able to determine the cable length between
the local terminal equipment and the DSX-3/STSX-1
Cross-Connect Patch-Panel. The cable length be-
tween the local terminal equipment and the DSX-3/
STSX-1 Cross-Connect Patch Panel ranges between
0 and 450 feet.
It is extremely unlikely that the system installation
personnel will know the cable length between the
DSX-3/STSX-1 Cross-Connect Patch-Panel and the
remote terminal equipment. Therefore, we recom-
mend that the Receive Equalizer be enabled by set-
ting the REQEN_(n) input pin or bit-field to “1”.
The only time that the Receive Equalizer should be
disabled is when there is an off-chip equilizer in the
Receive path between the DSX-3/STSX-1 Cross-
Connect and the RTIP_(n)/RRING_(n) input pins, or
in applications where the Receiver is directly monitor-
ing the transmit output signal directly.
3.2.1.2
Design Considerations for E3 Applica-
tions
In E3 System installation, it is recommended that the
Receive Equalizer of the XRT73LC04A be enabled
by pulling the REQEN_(n) input pins “High” or by set-
ting the REQEN_(n) bit-fields to “1”.
N
OTE
:
The results of extensive testing indicates that when
the Receive Equalizer is enabled, the XRT73LC04A is
capable of receiving an E3 line signal with anywhere from 0
to 12dB of cable loss over the Industrial Temperature
range.
Design Considerations for E3 Applications or if
the Overall Cable Length is known
If during System Installation the overall cable length
is known, then in order to optimize the performance
of the XRT73LC04A in terms of receive intrinsic jitter,
etc., enable or disable the Receive Equalizer based
upon the following recommendations:
The Receive Equalizer should be turned ON if the
Receive Section of a given channel is going to re-
ceive a line signal with an overall cable length of 300
feet or greater. Conversely, turn OFF the Receive
Equalizer if the Receive Section of a given channel is
going to receive a line signal over a cable length of
less than 300 feet.
N
OTES
:
1. If the Receive Equalizer block is turned ON when it
is receiving a line signal over short cable length,
the received line signal may be over-equalized
which could degrade performance by increasing
the amount of jitter that exists in the recovered data
and clock signals or by creating bit-errors
2. The Receive Equalizer has been designed to
counter the frequency-dependent cable loss that a
line signal experiences as it travels from the trans-
mitting terminal to the receiving terminal. However,
the Receive Equalizer was not designed to counter
flat loss where all of the Fourier frequency compo-
nents within the line signal are subject to the same
amount of attenuation. Flat loss is handled by the
AGC block.
Disable the Receive Equalizer block by doing either
of the following.
a. Operating in the Hardware Mode
Setting the REQEN_(n) input pin “Low".
b. Operating in the HOST Mode
Writing a "0" to the REQEN_(n) bit-field within Com-
mand Register CR2, as illustrated below.
COMMAND REGISTER CR-2(n)
D4
D3
D2
D1
D0
Reserved
Reserved
ALOSDIS_(n)
DLOSDIS_(n)
REQEN_(n)
X
X
X
X
0
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| XRT73LC04AIV | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73R06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73R06IB | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73R12 | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73R12IB | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73LC04A_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04AES | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC04AIV | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73LC04AIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 4-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73R06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
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